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General information for Digital Down and Digital Up Converter

Hello,

I am looking for general information on TI's DDC and DUC products are there any references?

Thanks,

Radio Joe

 

  • Hello,

    There is a general topic DDC and DUC fundamental guide, that is attached.

     Please send any questions or comments regarding this guide.

    Regards,

    Joe Quintal

    Application Engineer

    Wireless Digital Radio Products

    Texas Instruments

     

    DDCDUC Fundamentals_030205.zip
  • Hello:

    Is there a similar DDC/DUC guide that is customized for the capabilities of the GC6016.  So far the only info I have been able to find are the data sheet and the EVM manual.

    All input is appreciated.

    Larry Van Der Jagt

  • Hello,

    There is not an updated DDC / DUC application guide specifically for the GC533x and GC6016 family of devices.  I have attached a general presentation, and provided some

    additional comments.  The GC533x, and GC6016 have an Rx block down converter, 4 DDUCs, a Crest Factor Reduction block, (GC533x only) a Digital Predistortion block, A Bulk Tx Upconverter, an LVDS baseband interface, several different data converter interfaces. 

    In general the signal processing IQ rate to bandwidth supports 80% bandwidth in the Rx block down conversion, and Tx upconversion blocks.  If the stopband rejection is relaxed these blocks can support upto 90% bandwidth.

    The interfaces to the Rx block down converter (distributor), and CFR block through the sum chain, support an interleaved IQ bus.  Typically 1 or 2 processing bands are used for a receive antenna.  In the case of the transmit direction, the sumchain is used to combine several DDUCs' channels. 

    In the DDUC the architecture is that one direction DDC or DUC is supported at configuration time.  The DDUC to baseband interface supports a repeater crossbar Rx to Tx, or direct connection to the Baseband LVDS interfaces.  The PFIR and Resampler support 75% bandwidth, depending on the number of available PFIR taps, number of channels in the DDUC, and the desired stopband rejection.  The PFIR must provide droop compensation for the Resampler at more than 75% bandwidth, and the CIC sections.  In the DDUC if 1 or 2 channels are used the CIC filters are bypassed.  If there are 2-4 channels in the DDUC, the CIC can have a ratio of 2.  If there are 6-12 channels in the DDUC, the CIC can have a ratio of 3.  One DDUC can support 1, 2, 4, 6, 8, or 12 channels.  One resampler ratio is used to translate the PFIR output rate, to the CIC input rate.  The common Resampler - CIC rate is used for multimode support across multiple DDUCs.

    The PFIR is designed with a Low Pass filter for normal use, and wireless standards that do not require special equalization or pulse shaping.  The WCDMA, TDSCDMA, and special standards that require Root Raised Cosine pulse shaping, can also be utilized.  The PFIR supports symmetric odd number of taps, and non symmetric odd number of taps.   The cmd5330 tool indicates the number of PFIR taps for the number of channels used, and the PFIR input rate to DDUC clock rate. 

    The PFIR can have a ratio of 1 or 2.   2 is preferable to reduce the Resampler bandwidth.  The resampler adapts the ratio from the CIC to the PFIR.   The CIC has a 7 stage differential delay of 1, ratio of 1, 2, or 3.   

    Regards,

    Radio Joe

     

     

     

     

     

    5330_6016_overview_051711.pdf