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AWR1243BOOST: Unsuccessful attempt to configure device using FPGA interface over SPI

Arnaud Phelipot
Prodigy 40 points
Part Number: AWR1243BOOST
Other Parts Discussed in Thread: DCA1000EVM, , AWR1243, UNIFLASH

Hi,

I was unsuccessful to communicate through SPI based with AWR1243BOOST board based on a developed IP. My attempt is presently only to send CNYS + 6xFFFF to get out of HOSTIRQ high state. So I first consider the DCA1000EVM + AWR1243 and spied the SPI signals and as expected from other e2e post awr1243-question-about-spi-timing-protocol that data from master (MOSI signal) is evaluated by slave (AWR1243) on rising edge. Can you confirm?

I took care of inserting a delay of at least 2 SPI clock cycles before emitting 16 clock cycles and 16 bits MOSI data. In between CS signal was up for a long enough time (much more than 2 equivalent SPI clock cycles).

HW was configured as done with DCA1000EVM, with same SOP jumpers. The only difference is coming from the MSS and RSS loaded files which were not loaded to stand alone 1243BOOST board connected to FPGA board. Could this be the issue?

Could you give me a full explanation of the successive steps to do for the boot up sequence (not only the SPI transactions but also the previous steps).

Best regards

Nota: Half words were reverted as exposed in the Radar Interface Control Document.

  • 0
    TI__Guru*** 148584 points

    Hi,

    Please give us some time to check with extended team

    thank you

    Cesar

  • 0 in reply to Cesar
    Prodigy 40 points

    Thank you. As said I captured the sequence on the DCA1000EVM + AWR1243BOOST. I could see the IRQ signal going low. I had a jumper on SOP0 pin header only.

    Same configuration between my FPGA board and a brand new AWR1243BOOST kept IRQ high. Do I have to use a pre flashed AWR1243BOOST board by DCA1000EVM?

    Again if you have a step by step boot up sequence up to IRQ low for this board will be helpful for me to ensure I did not skip a step.

    Thks

  • +1 in reply to Arnaud Phelipot
    TI__Guru 69960 points

    Hi,

    I would recommend you to refer the mmWave DFP example which exemplifies the usage of API call along with FW download (boot up) sequence.

    And you must need to download the Patch file (c:\ti\mmwave_dfp_01_02_06_03\firmware\xwr12xx_metaImage.h) to AWR1243 over SPI after it powers up (refer example).

    Section 9 shows the API flow diagram - https://software-dl.ti.com/ra-processors/esd/MMWAVE-DFP/01_02_06_03/exports/mmwave_dfp_user_guide.pdf 

    Here is power supply sequence (Section 5.9), MibSPI timing condition (section 5.9.4.1), Typical SPI communication (5.9.4.2)

    https://www.ti.com/lit/ds/symlink/awr1243.pdf?ts=1632302739526&ref_url=https%253A%252F%252Fwww.google.com%252F

    On AWR1243BOOST: you need to connect only one jumper on SOP0 pin for functional mode.

    I see that you are using FPGA board to connect with AWR1243BOOT EVM, so I assume that FPGA board communicates to AWR1243 over SPI+HostIRQ and have LVDS/CSI-2 interface connected for Raw ADC data capture?

    Could you tell me at what step you are able to reach in the FPGA application while powering up and communicating with AWR1243 over SPI? 

    Regards,

    Jitendra

  • 0 in reply to Jitendra Gupta
    Prodigy 40 points

    Thank you for your reply,

    My current design is really simple it is a bridge on FPGA to SPI, triggered for each half word (16 bits sequence) to be sent by a control I exposed on my computer. At this time I don't need to collect data on LVDS/CSI2, I only want to see the IRQ signal low after a CNYS command, so my FPGA is not yet configured with the data in IP.

    Based on your reply I have some other questions:

    1) MSS and RSS are internal firmware for AWR1243 but do we must load them at each and every power up of AWR1243BOOST or are they stored in a memory on the board or in the AWR1243 chip after first loading when the board is powered up for the first time?

    2) In section 4.1 of mmWave DFP User Guide, it is said that EVM board exposed a UART interface for downloading the firmware in serial flash (so this is a flash? with data retention of the firmware and so on?)

  • 0 in reply to Arnaud Phelipot
    Prodigy 40 points

    Update: I used mmWaveStudio to do the first steps of AWR12xx and DCA1000 configuration. I skipped the SPI connect step to use my SPI interface and it seemed to be Ok.For the moment I can send CNYS pattern, see IRQ going low and get the response  (0xDCBA 0xABCD...).

    I have seen that IRQ is going high as soon as the MSS is loaded. Does it mean that host controller always has to load the MSS? Could we have auto load at power on for this FW?

  • +1 in reply to Arnaud Phelipot
    TI__Guru 69960 points
    Arnaud Phelipot said:
    1) MSS and RSS are internal firmware for AWR1243 but do we must load them at each and every power up of AWR1243BOOST or are they stored in a memory on the board or in the AWR1243 chip after first loading when the board is powered up for the first time?

    If you are AWR1243BOOST, then you can flash the firmware to the device, so at every boot FW is loaded as device powers up.

    Use UniFlash to flash C:\ti\mmwave_dfp_01_02_06_03\firmware\xwr12xx_metaImage.bin to AWR1243BOOT EVM.

    Arnaud Phelipot said:
    2) In section 4.1 of mmWave DFP User Guide, it is said that EVM board exposed a UART interface for downloading the firmware in serial flash (so this is a flash? with data retention of the firmware and so on?)

    Answered above.

    Arnaud Phelipot said:
    I have seen that IRQ is going high as soon as the MSS is loaded. Does it mean that host controller always has to load the MSS? Could we have auto load at power on for this FW?

    With the flash mode, FW will be loaded at every boot. So from the FPGA (host app) you can directly jump to configure the device.

    I see that you are able to read the first power up async-event (after first HostIRQ high), please refer the DFP example to further configure the device.