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AWR2243BOOST: Incorrect Sync data received from AWR2243

Part Number: AWR2243BOOST
Other Parts Discussed in Thread: AWR2243

Hello Jitendra,

I followed the procedure given in the thread: AWR2243BOOST: mmwave Device Power on failed for deviceMap1 with error -8 in AWR Single Chip setup with Jetson AGX - Sensors forum - Sensors - TI E2E support forums

I am able to get to step 7 where HOSTIRQ is brought low . Here is a wave form capture of just that:

But the AWR device doesnot send a response on HostIrq is low, instead sends a response of FFFE after interrupt goes high again.

Could you please clarify this issue.

Thanks and Regards

Vignesh

  • Hello Vignesh, 

    Thankyou for reaching out on TI E2E support forums. 

    Our expert on this issue (Jitendra) is out of office this week. Please give us some time to investigate your issue and we will get back to you on this next week. 

    Hope that's okay. Thankyou for your patience. 

    Regards,

    Ishita

  • Hi Vinesh,

    I see that HostIRQ goes up again after you write the CNYS pattern (0x5678 0x8765...)

    I hope you have taken care of all the requirement for SPI communication as shown in below snapshot from ICD (interface control document)

    Regards,

    Jitendra

  • Hello Jitendra,

    I ensured that the requirements are taken care. I will anyway check again.

    But is that the only reason that could pull the Host Interrupt line high, or could there be any other issue too.

    It would be better if you could share any working log with the Host Interrupt line and nReset line along with the SPI communication for verification.

    Thanks and Regards

    Vignesh.

  • Attached is the working log captured from Logic analyzer

    /cfs-file/__key/communityserver-discussions-components-files/1023/1.-DevicePowerOn.logicdata.zip

    Look b/w A1 and A2 maker in this log.

  • Hello Jitendra,

    In the log provided by you:-

    Clock Frequency : 10MHz (100ns)
    Time between consecutive CS low : 75ns
    Time between CS low and Clock update : 100ns

    These timing values do not satisfy the constraints provided in the Interface control document.

    In my measurement :

    Clock Frequency : 10MHz (100ns)
    Time between consecutive CS low : 84 microseconds
    Time between CS low and Clock update : 100ns

    Do the timing constraints really matter ? since these are not satisfied in the measurement you had provided also.
    Operational mode and Byte length constraints are the same.

    I could not understands the scenario, why the Host Interrupt goes high again and there is no data received when the Host Interrupt is low.

    Regards

    Vignesh

  • Hi Vignesh,

    Reviewing you first snapshot again, I realized that HostIRQ low to High is taking more than 15msec that is unreasonable time from AWR device except device gets reset during this time.

    And if all the read data after that from zero then definitely device gets reset (and post reset HostIRQ goes high again) else that SPI read data should be some non-zero value which is response of written CNYS pattern (0x5678 0x8765 ....).

    I assume this is your customer board with AWR2243 device. Could you confirm that you have follow all the guideline as mentioned in device schematic and the power schemes?

    And please probe on power rails during this error to confirm if device gets reset b/w HostIRQ low and high.

    Regards,

    Jitendra