Other Parts Discussed in Thread: LP87745,
Hi team,
Customer is using SPIA port for PMIC LP87745 control, it was SPIB on TI EVM.
For TIEVM SPIB test, everything is good, read out 0X96 from 0x01 address. But for customize board, they only change the SPIB to SPIA in syscfg.
Then AWR2944 can only read 0x00 from address 0x01. But the 0x96 can be seem on the oscilloscope on the MISO line.
So what's the difference between the SPIA config and SPIB config? i had also attach the register value from device.
Please see information below.
logic analyzer screenshot to read 0X01 address in LP87745, 0X96 can be seemed in the MISO line.
register comparison
SPIB register value which is good and evaluated on TIEVM
MSS_SPIB MSS SPIB Module Registers SPIGCR0 0x00000001 SPI / MibSPI Global Control Register 0 [Memory Mapped] SPIGCR1 0x00000003 SPI / MibSPI Global control register 1 [Memory Mapped] SPIINT0 0x0000005F SPI / MibSPI Interrupt Enable Register [Memory Mapped] SPILVL 0x0000005F SPI / MibSPI Interrupt Level Register [Memory Mapped] SPIFLG 0x00000000 SPI / MibSPI Flag Register [Memory Mapped] SPIPC0 0x01010E01 SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented. it is a mirror of Bit11. Any write to Bit 24 will be reflected on Bit11 and when Bit 24 & Bit 11 simultaneously written, the value of Bit11 will control the SOMI pin. Read value of Bit 24 always reflects the Bit 11 value. This is true for the Bit 24 & Bit 11 of all of SPIPC0 to SPIPC9 registers. Same is true for SIMO pin with Bit16 & Bit 10 of SPIPC0 to SPIPC9 registers. [Memory Mapped] SPIPC1 0x00000000 SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR [Memory Mapped] SPIPC2 0x00000101 SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN [Memory Mapped] SPIPC3 0x00000000 SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT [Memory Mapped] SPIPC4 0x00000000 SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET [Memory Mapped] SPIPC5 0x00000000 SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR [Memory Mapped] SPIPC6 0x00000000 SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR [Memory Mapped] SPIDAT0 0x00000000 SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI. It is only accessible in compatibility mode. [Memory Mapped] SPIDAT1 0x00000000 SPI / MibSPI Transmit Data Register 1 When this register is read, contents of internal buffer register TXBUF which holds the latest written data will be returned. [Memory Mapped] SPIBUF 0x80000000 SPI / MibSPI Receive Buffer Register [Memory Mapped] SPIEMU 0x80000000 SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only. Read operation on this register under any mode will not have any impact on the status of this or any other registers. [Memory Mapped] SPIDELAY 0x05050000 SPI / MibSPI Delay Register [Memory Mapped] SPIDEF 0x00000007 SPI / MibSPI Default Chip select Register [Memory Mapped] SPIFMT0 0x0001F908 SPI / MibSPI Data Format Register 0 [Memory Mapped] SPIFMT1 0x00001208 SPI / MibSPI Data Format Register 1 [Memory Mapped] SPIFMT2 0x00001208 SPI / MibSPI Data Format Register 2 [Memory Mapped] SPIFMT3 0x00001208 SPI / MibSPI Data Format Register 3 [Memory Mapped] TGINTVECT0 0x00000000 SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0 [Memory Mapped] TGINTVECT1 0x00000000 SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1 [Memory Mapped] SPIPC9 0x00000000 SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL [Memory Mapped] SPIPMCTRL 0x00000000 SPI/MibSPI Parallel/Modulo Mode Control Register [Memory Mapped] MIBSPIE 0x00000500 MibSPI Enable Register [Memory Mapped] TGITENST 0x00FF0000 MibSPI Transfer Group Interrupt Enable Set Register [Memory Mapped] TGITENCR 0x00FF0000 MibSPI Transfer Group Interrupt Enable Clear Register [Memory Mapped] TGITLVST 0x00010000 MibSPI Transfer Group Interrupt Level Set Register [Memory Mapped] TGITLVCR 0x00010000 MibSPI Transfer Group Interrupt Level Clear Register [Memory Mapped] TGINTFLAG 0x00000001 Transfer Group Interrupt Flag Register [Memory Mapped] TICKCNT 0x00000000 Tick Count Register [Memory Mapped] LTGPEND 0x00000200 Last Transfer Group End Pointer [Memory Mapped] TG0CTRL 0x40700000 MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16. Depending on the implementation the number of transfer groups and hence the number of transfer group control register may vary. Each transfer group can be configured via one dedicated control register. The register description below shows one exemplary control register(x) which is identical for all transfer groups. E.g. the control register for transfer group 2 is named “TG2CTRL” and is located at address base0+98h+4*2. [Memory Mapped] TG1CTRL 0x00000300 MibSPI Transfer Group Control Register [Memory Mapped] TG2CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] TG3CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] TG4CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] TG5CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] TG6CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] TG7CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] DMA0CTRL 0x82100000 MibSPI DMA Channel Control Register [Memory Mapped] DMA1CTRL 0x00000000 MibSPI DMA Channel Control Register [Memory Mapped] DMA2CTRL 0x00000000 MibSPI DMA Channel Control Register [Memory Mapped] DMA3CTRL 0x00000000 MibSPI DMA Channel Control Register [Memory Mapped] DMA4CTRL 0x00000000 MibSPI DMA Channel Control Register [Memory Mapped] ICOUNT0 0x00000000 MibSPI DMAxCOUNT [Memory Mapped] ICOUNT1 0x00000000 MibSPI DMAxCOUNT [Memory Mapped] ICOUNT2 0x0000 MibSPI DMAxCOUNT [Memory Mapped] ICOUNT3 0x00000000 MibSPI DMAxCOUNT [Memory Mapped] ICOUNT4 0x00000000 MibSPI DMAxCOUNT [Memory Mapped] DMACNTLEN 0x00000000 DMA LARGE COUNT register [Memory Mapped] PAR_ECC_CTRL 0x050A0005 Parity/ECC Control Register [Memory Mapped] PAR_ECC_STAT 0x00000000 Parity/ECC Status Register [Memory Mapped] UERRADDR1 0x00000200 Uncorrectable Parity or double bit ECC error Address Register - RXRAM [Memory Mapped] UERRADDR0 0x00000000 Uncorrectable Parity or double bit ECC error address register - TXRAM [Memory Mapped] RXOVRN_BUF_ADDR 0x00000200 Receive RAM Overrun Buffer Address Register [Memory Mapped] IOLPBKTSTCR 0x00000000 SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins. It also controls whether loop-back should be digital or analog ones in this test mode. In addition it contains control bits to induce some of the error condition into the module. These are to be used for test purpose only. All the control/status bits in this register are valid only when IO LPBK TST ENA field is set to “1010”. [Memory Mapped] EXTENDED_PRESCALE1 0x001200F9 SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves. This is an extension of SPIFMT0 and SPIFMT1 registers. For example, EPRESCALE_FMT1(7:0) of EXTENDED_PRESCALE1 and PRESCALE1(7:0) of SPIFMT1 register will always reflect the same contents. Similarly EPRESCALE_FMT0(7:0) and PRESCALE0(7:0) of SPIFMT0 reflect the same contents. [Memory Mapped] EXTENDED_PRESCALE2 0x00120012 SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves. This register is an extension of SPIFMT2 and SPIFMT3 registers. For example, EPRESCALE_FMT2(7:0) of EXTENDED_PRESCALE2 and PRESCALE2(7:0) of SPIFMT2 register will always reflect the same contents. Similarly EPRESCALE_FMT3(7:0) and PRESCALE3(7:0) of SPIFMT3 reflect the same contents. [Memory Mapped] ECCDIAG_CTRL 0x0000000A ECC Diagnostic Control register [Memory Mapped] ECCDIAG_STAT 0x00000000 ECC Diagnostic Status register [Memory Mapped] SBERRADDR1 0x00000200 Single Bit Error Address Register - RXRAM [Memory Mapped] SBERRADDR0 0x00000000 Single Bit ECC Error Address Register - TXRAM [Memory Mapped] SPIREV 0x4A051309 SPI / MibSPI Revision ID Register [Memory Mapped]
SPIA register value which is issued and read out data is 0x00 from LP87745 address 0x01
MSS_SPIA MSS SPIA Module Registers SPIGCR0 0x00000001 SPI / MibSPI Global Control Register 0 [Memory Mapped] SPIGCR1 0x01000003 SPI / MibSPI Global control register 1 [Memory Mapped] SPIINT0 0x0000005F SPI / MibSPI Interrupt Enable Register [Memory Mapped] SPILVL 0x0000005F SPI / MibSPI Interrupt Level Register [Memory Mapped] SPIFLG 0x00000200 SPI / MibSPI Flag Register [Memory Mapped] SPIPC0 0x01010E01 SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented. it is a mirror of Bit11. Any write to Bit 24 will be reflected on Bit11 and when Bit 24 & Bit 11 simultaneously written, the value of Bit11 will control the SOMI pin. Read value of Bit 24 always reflects the Bit 11 value. This is true for the Bit 24 & Bit 11 of all of SPIPC0 to SPIPC9 registers. Same is true for SIMO pin with Bit16 & Bit 10 of SPIPC0 to SPIPC9 registers. [Memory Mapped] SPIPC1 0x00000000 SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR [Memory Mapped] SPIPC2 0x01010F01 SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN [Memory Mapped] SPIPC3 0x00000000 SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT [Memory Mapped] SPIPC4 0x00000000 SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET [Memory Mapped] SPIPC5 0x00000000 SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR [Memory Mapped] SPIPC6 0x00000000 SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR [Memory Mapped] SPIDAT0 0x00000000 SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI. It is only accessible in compatibility mode. [Memory Mapped] SPIDAT1 0x00000000 SPI / MibSPI Transmit Data Register 1 When this register is read, contents of internal buffer register TXBUF which holds the latest written data will be returned. [Memory Mapped] SPIBUF 0x80000000 SPI / MibSPI Receive Buffer Register [Memory Mapped] SPIEMU 0x80000000 SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only. Read operation on this register under any mode will not have any impact on the status of this or any other registers. [Memory Mapped] SPIDELAY 0x05050000 SPI / MibSPI Delay Register [Memory Mapped] SPIDEF 0x00000001 SPI / MibSPI Default Chip select Register [Memory Mapped] SPIFMT0 0x0001DB08 SPI / MibSPI Data Format Register 0 [Memory Mapped] SPIFMT1 0x00001208 SPI / MibSPI Data Format Register 1 [Memory Mapped] SPIFMT2 0x00001208 SPI / MibSPI Data Format Register 2 [Memory Mapped] SPIFMT3 0x00001208 SPI / MibSPI Data Format Register 3 [Memory Mapped] TGINTVECT0 0x00000000 SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0 [Memory Mapped] TGINTVECT1 0x00000000 SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1 [Memory Mapped] SPIPC9 0x00000000 SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL [Memory Mapped] SPIPMCTRL 0x00000000 SPI/MibSPI Parallel/Modulo Mode Control Register [Memory Mapped] MIBSPIE 0x00000501 MibSPI Enable Register [Memory Mapped] TGITENST 0x00FF00FF MibSPI Transfer Group Interrupt Enable Set Register [Memory Mapped] TGITENCR 0x00FF00FF MibSPI Transfer Group Interrupt Enable Clear Register [Memory Mapped] TGITLVST 0x00000000 MibSPI Transfer Group Interrupt Level Set Register [Memory Mapped] TGITLVCR 0x00000000 MibSPI Transfer Group Interrupt Level Clear Register [Memory Mapped] TGINTFLAG 0x00000000 Transfer Group Interrupt Flag Register [Memory Mapped] TICKCNT 0x00000000 Tick Count Register [Memory Mapped] LTGPEND 0x0000FF00 Last Transfer Group End Pointer [Memory Mapped] TG0CTRL 0x40700000 MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16. Depending on the implementation the number of transfer groups and hence the number of transfer group control register may vary. Each transfer group can be configured via one dedicated control register. The register description below shows one exemplary control register(x) which is identical for all transfer groups. E.g. the control register for transfer group 2 is named “TG2CTRL” and is located at address base0+98h+4*2. [Memory Mapped] TG1CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] TG2CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] TG3CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] TG4CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] TG5CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] TG6CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] TG7CTRL 0x00000000 MibSPI Transfer Group Control Register [Memory Mapped] DMA0CTRL 0x00000000 MibSPI DMA Channel Control Register [Memory Mapped] DMA1CTRL 0x00000000 MibSPI DMA Channel Control Register [Memory Mapped] DMA2CTRL 0x00000000 MibSPI DMA Channel Control Register [Memory Mapped] DMA3CTRL 0x00000000 MibSPI DMA Channel Control Register [Memory Mapped] DMA4CTRL 0x00000000 MibSPI DMA Channel Control Register [Memory Mapped] ICOUNT0 0x00000000 MibSPI DMAxCOUNT [Memory Mapped] ICOUNT1 0x00000000 MibSPI DMAxCOUNT [Memory Mapped] ICOUNT2 0x0000 MibSPI DMAxCOUNT [Memory Mapped] ICOUNT3 0x00000000 MibSPI DMAxCOUNT [Memory Mapped] ICOUNT4 0x00000000 MibSPI DMAxCOUNT [Memory Mapped] DMACNTLEN 0x00000000 DMA LARGE COUNT register [Memory Mapped] PAR_ECC_CTRL 0x050A0005 Parity/ECC Control Register [Memory Mapped] PAR_ECC_STAT 0x00000000 Parity/ECC Status Register [Memory Mapped] UERRADDR1 0x00000200 Uncorrectable Parity or double bit ECC error Address Register - RXRAM [Memory Mapped] UERRADDR0 0x00000000 Uncorrectable Parity or double bit ECC error address register - TXRAM [Memory Mapped] RXOVRN_BUF_ADDR 0x00000200 Receive RAM Overrun Buffer Address Register [Memory Mapped] IOLPBKTSTCR 0x00000000 SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins. It also controls whether loop-back should be digital or analog ones in this test mode. In addition it contains control bits to induce some of the error condition into the module. These are to be used for test purpose only. All the control/status bits in this register are valid only when IO LPBK TST ENA field is set to “1010”. [Memory Mapped] EXTENDED_PRESCALE1 0x001200DB SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves. This is an extension of SPIFMT0 and SPIFMT1 registers. For example, EPRESCALE_FMT1(7:0) of EXTENDED_PRESCALE1 and PRESCALE1(7:0) of SPIFMT1 register will always reflect the same contents. Similarly EPRESCALE_FMT0(7:0) and PRESCALE0(7:0) of SPIFMT0 reflect the same contents. [Memory Mapped] EXTENDED_PRESCALE2 0x00120012 SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves. This register is an extension of SPIFMT2 and SPIFMT3 registers. For example, EPRESCALE_FMT2(7:0) of EXTENDED_PRESCALE2 and PRESCALE2(7:0) of SPIFMT2 register will always reflect the same contents. Similarly EPRESCALE_FMT3(7:0) and PRESCALE3(7:0) of SPIFMT3 reflect the same contents. [Memory Mapped] ECCDIAG_CTRL 0x0000000A ECC Diagnostic Control register [Memory Mapped] ECCDIAG_STAT 0x00000000 ECC Diagnostic Status register [Memory Mapped] SBERRADDR1 0x00000200 Single Bit Error Address Register - RXRAM [Memory Mapped] SBERRADDR0 0x00000000 Single Bit ECC Error Address Register - TXRAM [Memory Mapped] SPIREV 0x4A051309 SPI / MibSPI Revision ID Register [Memory Mapped]
code:
retVal = BoardDiag_checkPMIC(gMibspiHandle[CONFIG_MIBSPI0]);
int32_t BoardDiag_checkPMIC(MIBSPI_Handle handle)
{
uint8_t count;
uint8_t regValue;
uint8_t regAddr=1;
for(count=0;count<100;count++)
{
regValue = BoardDiag_mcanReadPmicReg(handle,regAddr);
printf("Read Register[%x] = 0x%x\n",regAddr,regValue);
regAddr++;
}
return 0;
}
static uint8_t BoardDiag_mcanReadPmicReg(MIBSPI_Handle handle, uint8_t regOffset)
{
volatile uint8_t tx[APP_MSGSIZE];
volatile uint8_t rx[APP_MSGSIZE];
volatile MIBSPI_Transaction transaction;
memset(&transaction, 0, sizeof(transaction));
/* Configure Data Transfer */
transaction.count = APP_MSGSIZE;
transaction.txBuf = (void *)tx;
transaction.rxBuf = (void *)rx;
transaction.slaveIndex = 0;
/* Single read transmissions consists of 24bit:
* Bits 0-7 : Register Address
* Bits 8-10 : Page address for the register
* Bit 11 : For Read, value should be 1
* Bits 12-15: Reserved
* Bits 16-23: Value Read from the PMIC
*/
tx[0] = regOffset;
tx[1] = 0x10;
tx[2] = 0;
CacheP_wbInv((void *) tx, APP_MSGSIZE, CacheP_TYPE_ALL);
/* Start Data Transfer */
MIBSPI_transfer(handle, &transaction);
/* Invalidate the receive buffer */
CacheP_inv((void *) rx, APP_MSGSIZE, CacheP_TYPE_ALL);
return rx[2];
}
Thanks.
Wesley
