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TMAG5170-Q1: 12-byte SPI communication

Part Number: TMAG5170-Q1

I'm trying to Read and Write to the chip in a single SPI communications operation. In short, I am trying to send chunks of 4 bytes sequentially as 12 bytes in a row. When I do this, the chip does not seem to actually update its internal registers. I would like to confirm or understand this better...? Does the CS line need to go high between 4 byte chunks? 

  • Chad, 

    Thanks for reaching out.  CS should remain low during the entire 32 bit write sequence.  It is not uncommon to see each transaction split into 4 bytes with a very short pause between each byte.  The CS line must return high at the end of each command, otherwise the device will see this as a clocking error with too many bits in each transaction.

    What is commonly the cause for the device to not latch writes is a CRC error.  CRC is a transmission quality check to ensure no bits are incorrectly received.  Each transaction requires calculation of the final 4 bits to be written based on the preceding 28 bits.  This is on by default, but can be disabled by writing  x0F000407.  

    More details about CRC can be found in this thread: