IWR6843: Cs chip select exception during SPIA interface Master communication, with a stable 8 us cycle interference signal

Hi team,

Here's an issue from the customer may need your help:

The customer made a board based on the IWR6843AOP.

The CS chip-select signal was found to be abnormal when using SPIA (master, 1-MHz clock) communication with an external slave, and there was always a 8us cycle of signal interference during low-hold, resulting in unexpected slave receive data.

Disconnect the slave and test the chip select signal of the board and find that the signal interference is still happen. There are no corresponding sources of interference in the board, and the PCB layout has been reviewed without issue.

Testing was performed using the IWR6843AOPEVM instead and found that the SPI chip select signal still had 8us interference in the same firmware. With the IWR6843AOP chip as master, is the above behavior expected for SPI communication? Or is there a problem with the customer's use?

There is no problem in the DCA1000EVM capture mode to adjust the parameters of the radar FE via SPIA, but the radar is on the Slave side, so the above problem cannot be demonstrated.

Could you help check this case? Thanks.

Best Regards,

Cherry