[FAQ] What are the benefits and SW migration effort moving to AWR2944 from AWR1642/AWR1843?

Q: I'm using AWR1843 and now planning to move to AWR2944, what are benefit and migration steps to move my software to AWR2944?

Please find below high level of SW migration guide from 1^st Gen mmWave Sensor (AWR1642/AWR1843) to 2^nd Gen mmWave Sensor (AWR294x).

System config changes in AWR 2^nd generation from 1^st generation devices

         There are significant improvements in terms of the system configuration used for 2^nd generation of AWR devices like AWR2944. First the system as a whole got updated with HWA2.1/2.0 in 2^nd gen AWR devices (HWA 2.0 is used in AM273x processor and AWR2944 ES1.0 while AWR2944 ES2.0 has HWA2.1 version). HWA2.0/2.1 in 2^nd gen AWR devices runs at 300MHz, a local maxima engine, better interference detection and mitigation capabilities, better CFAR engine, better FFT engine over HWA1.1 (which runs at 200MHz) in 1^st gen AWR devices (like AWR1843). Also, the DSP used in 2^nd gen AWR devices c66x DSP  over c674x DSP  in 1^st gen AWR devices provides lot more performance improvement based on compute, parallelization, performance etc. 

         With these improvements, the 2^nd generation of AWR devices can implement better algorithms like DDMA (Doppler Division Multiple Access) for covering R79 NCAP regulations which can detect cars up to 220m and bikes up to 170m in comparison with 1^st generation devices. There are significant changes in the signal processing chain to achieve the DDMA chain implementation. One of the major improvements was the use of HWA2.x effectively with minimum DSP intervention and parallelism between HWA and DSP to achieve the same.

         The major change while porting from 1^st generation to 2^nd generation AWR devices is that in the 1^st generation of devices it has ADCBuf memory mapped to HWA input memory (where EDMA transfer is not required after chirp ADC data is available), however in the 2^nd generation devices, this feature is not available and EDMA transfer is needed based on ADC capture complete interrupt (though this transfer time can be in parallel to HWA processing).  Other changes while porting from 1^st generation to 2^nd generation of AWR devices could be in terms of software where there are few API changes for the HWA and EDMA drivers.

OOB (Out of box demo) Signal processing chain change

         The signal processing chain has changed a quite lot from 1^st gen AWR devices to the 2^nd generation AWR devices. Unlike the 1^st generation devices which have the TDM-MIMO chain wherein only 1-Tx chirps at a single time instant, the 2^nd generation AWR devices have all the 4-Tx chirping at the same time with a phase shift. This is achieved with a unique cyclic phase sequence using the TX phase shifters. As simultaneous Tx transmit, higher SNR is achieved when compared to TDM-MIMO chain in 1^st generation AWR devices with easy Vmax extension for 2^nd generation devices.                 

         As mentioned previously, the 2^nd generation of AWR devices have the capability to perform the signal processing operations utilizing HWA2.x alone which will be faster and reducing the load on c66x DSP. Hence in 2^nd generation, we have used only HWA for signal processing operations.

          As the DDMA (Doppler Division Multiple Access) signal chain (in 2^nd generation devices) needs more data (more chirps/ADC samples) to get the required performance, there is a need for additional step of compression after range-FFT and decompression before Doppler FFT. In the range processing, additional steps of DC estimation and subtraction (due to DC removal block in 2^nd gen over 1st gen), interference detection and mitigation (this block is enhanced from the 1^st generation due to I-only architecture of 2^nd generation devices), and finally the compressed radar cube (after 1D-FFT) is stored in the L3 memory. Range processing block uses HWA and EDMA alone with no intervention of DSP.

         Before the Doppler processing, this compressed radar cube must be decompressed and then only 2D-FFT has to be applied. In this Doppler processing step, detection matrix, DDMA metric etc are calculated. Based on this, doppler demodulation is done which can help us figure out for an object which virtual antenna does it correspond for angle estimation step. This step of DDMA demodulation is done in DSP while the HWA does the steps of Doppler processing. Followed by this Azimuth FFT is done, then CFAR-OS in Doppler direction on Azimuth samples. The local maxima engine of HWA2x is leverage to perform local maxima on Azimuth samples in both range and doppler dimension. The intersection of peaks of local maxima and CFAR is taken as detected objects. This process of extracting object list is done by DSP while in parallel HWA might be performing Doppler/Azimuth stage. In addition to this, there is the range CFAR DPU (which is optional), which performs CFAR from detection matrix. If the range CFAR DPU is enabled then for estimation of point cloud information x, y and z, this has to be the intersection of peaks from Doppler-Azimuth DPU and range CFAR DPU else Doppler Azimuth DPU alone is used.

         Higher SNR and Doppler ambiguity removal (through empty band) makes the DDMA modulation scheme more robust than traditional TDM chain in 1^st generation devices.

HWA2.x key features over HWA 1.1

         The HWA2.x has the key feature of context-switching which allows user to switch to range processing operations in middle of doppler or azimuth processing chain operation when the trigger for next chirp available comes due to lesser frame idle time by the use of thread switching. The HWA2.0/2.1 can run two threads namely the high priority thread (context-switch state) and low-priority thread (default running state of HWA). This enables the user for more unique chirping schemes.

         The HWA2.0/2.1 supports 10-complex multiplication modes (with features as recursive windowing, frequency shifter with fine frequency increment), zero-insertion (filling of zeros at arbitrary locations - different from zero padding), channel combination etc

         In addition to this, HWA2.0/2.1 supports 3*2^N FFT, direct 2D-FFT computation and also advanced statistics block for local maxima and CFAR computation. The table in next page shows the key feature enhancements of HWA2.0/2.1 over HWA1.1 in 1^st generation devices.

Performance comparison between C66x DSP and C674x DSP

         On the C66x ISA, the vector processing capability is improved by extending the width of the SIMD instructions. The C674x DSP supports 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. C66x enhances these capabilities with the addition of SIMD instructions for 32-bit data allowing operation on 128-bit vectors.

References:

1. Technical reference manual (HWA v2.x)of AWR294x (link)
2. Radar Hardware Accelerator (HWA v1.1) user-guide (link)
3. mmWave MCU Plus SDK documentation (link)
4. TMS320C66X DSP CPU and instruction set (link)