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IWRL6432: IWRL6432AOP non-operation problem

Part Number: IWRL6432
Other Parts Discussed in Thread: AWRL6432AOP

Hello

We recently received five samples of the IWRL6432AOP. And five test boards were produced.

However, only two of the five units operate normally (image flashing and radar operation), and the remaining three units do not operate (image flashing does not work either). Here's what we checked:
1. Check UART communication: no problem
2. Since two units operate, there is no problem with the circuit configuration.

Next, here's what we did:
1. After flashing the image, I removed the flash memory from the board that was operating normally and assembled the removed memory onto the board that was not working.
2. And check that it is operating normally: It does not start from booting.

So we determined that the default boot loader was not included in the chip we received as a sample.

If you have any experience resolving situations like this, I would appreciate your suggestions on how to resolve them.
If the chip is the problem, I wonder if we can provide additional sample chips (AWRL6432AOP or IWRL6432AOP) from TI.

  • Hi Lee,

    Could you please share the device marking of the IWRL6432AOP devices not working. Also, could please confirm if the schematic was reviewed from TI; and what is the reference schematic used to develop the board.

    Regards

    Ankit

  • A photo of the non-functioning chip is below.

    We received the schematic of TI's AWRL6432AOP EVM from TI and designed the board using it as a reference.

  • Hi Lee,

    Could please connect to JTAG and read few registers address through CCS. 

    Please find attached the steps. CCS Debug for IWRL6432.pptx

    We can determine whether the device is trimmed or untrimmed by reading following memory address.

    25th Bit of EFUSE0_ROW_41 register (Memory address: 0x5A020094) or

    19th Bit of EFUSE0_ROW_53 (Memory address: 0x5A0200C4).

     

    If these bits are 1, then the devices are trimmed. Untrimmed otherwise.

    Also,

    SOP mode register (TOPSS_CTRL_SOP_MODE): 0x5b020008 (Flash mode should read 0x00000000, Functional Mode should read 0x00000001) 

    If you are unable to connect to JTAG. Please share your schematic and the Oscilloscope captures of VIOIN, SOP0 and SOP1 signals during NRESET release (please include RESET signal as well - 4 probe capture). Please check if VBGAP is coming up as 0.9V and the XTAL capacitors oscillating at 40MHz.

    Regards

    Ankit

  • Hi Ankit,

    Sorry for the late reply.

    JTAG does not connect. So, we captured the waveforms of VIOIN, SOP0, and SOP1 during NRESET release. The result is as shown in the following figure.
    And VBGAP is confirmed to be 0V, and 40 MHz Clock is no problem.

    Thank you.

    Regards

    Lee

  • Hi Lee,

    The boot up sequence appear to be correct. VIOIN and SOP signals are stable at the time of reset release; but VBGAP being LOW suggest boot up failure.

    Could you please elaborate "40 MHz Clock is no problem"? The 40MHz clock signals comes up after VBGAP (0.9V) is stable. Are you seeing 40MHz clock signals but not VBGAP ?

    Regards

    Ankit

  • Hello. Ankit

    “40 MHz Clock is no problem” was the wrong answer. sorry.
    We confirmed that 40 MHz Clock is not generated when VBGAP is 0V.

    Regards

    Ankit

  • Hi Lee,

    As we do not have JTAG connection, it is very difficult to root cause the issue as Oscilloscope captures for SOP signals appear to be correct. Can you please try replacing the device or check the board schematics that might cause this issue. We can do a schematic review for the same.

    Regards

    Ankit

  • Hello. Ankit.

    We also want to try replacing the chip.
    However, we only received 5 samples from TI, so there are no spares.

    Can I get additional samples of the IWRL6432AOP or AWRL6432AOP chip?

    Please answer about my question.
    Thank you.

  • Hi Lee,

    Can you please get in touch with the regional FAE or the marketing team for the same. I can assist you if you need any help in reaching out to them.

    Regards

    Ankit