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AWRL6432: Question on the wakeup source of deep sleep mode

Chris Meng
Mastermind 36485 points
Part Number: AWRL6432
Other Parts Discussed in Thread: SYSCONFIG

Hi,

I have some questions about the wakeup source of deep sleep mode. Would you pls help?

In TRM, I found below info.

1. What's meaning of CPU when both HCLK and FCLK are gated? Does it mean CPU deep sleep mode? 

2. The device deep sleep mode (most power saving mode) wake up sources are sleep counter, UART, SPI and GPIO. It doesn't mention that SYNC_IN can wakeup device from device deep sleep mode.

But in below post, it seems that SYNC_IN can also wakeup the device from device deep sleep mode. Would you pls help to double confirm?

https://e2e.ti.com/support/sensors-group/sensors/f/sensors-forum/1290399/awrl6432-deep-sleep-wakeup-source-enable

3. In above info, it says " The wakeup from UART, SPI or GPIO is the negative edge on these signals ", but in below register I saw the positive or negative edge can be selected for wakeup. So positive edge (rising edge) is also supported to wakeup device from device deep sleep mode if below register is set correctly(e.g. bit10 of WU_SOURCE_EN is set to 0) , right?

Thanks,

Chris

  • 0
    TI__Expert 6895 points

    Hey Chris,

    I'll answer your questions in order below:

    1. Yes, the CPU is in deep sleep mode when both HCLK and FCLK are gated as mentioned in Section 23.1.3.2 CPU/Device Sleep/Deepsleep of the TRM
    2. The device can wakeup using SYNC_IN as a source. You can also see the LPDS example in SDK 5.4 under <MMWAVE_LSDK_INSTALL_DIR>/examples/drivers/power/power_modes which supports SYNCIN_IO.

    3. You can select either positive (rising) or negative (falling) edges for GPIO or SYNC_IO using SysConfig. For UART and SPI, you can use the code below to configure the edge. Note: For the field name, use CSL_TOP_PRCM_WU_SOURCE_EN_WU_SOURCE_EN_UART_RX_EDGE for UART and CSL_TOP_PRCM_WU_SOURCE_EN_WU_SOURCE_EN_SPI_CS_EDGE for SPI.

      regVal = HW_RD_REG32(CSL_TOP_PRCM_U_BASE + CSL_TOP_PRCM_WU_SOURCE_EN);
      HW_SET_FIELD32(regVal, /*insert field name*/, /*insert field value*/); 
      HW_WR_REG32(CSL_TOP_PRCM_U_BASE + CSL_TOP_PRCM_WU_SOURCE_EN, regVal);

    Let me know if this answers your questions.

    Regards,

    Kristien