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Original question:

AWR2944: Disable DSP L1D Cache in SBL

AWR2944: Use part of the L1D memory as SRAM

Predrag Bratic
Prodigy 10 points
Part Number: AWR2944

Tool/software:

Hi,

We want to change L1D memory to use 16kB as cache and 16kB as SRAM. I have changed everything in code and linker to cover for this new section DSS_L1D but looks like DSS code stalls when run. Probably SBL also needs some changes.

I know that there is related question on this: AWR2944: Disable DSP L1D Cache in SBL - Sensors forum - Sensors - TI E2E support forums, but have some ambiguities:

- we have changed 

.l1dSize = CacheP_L1Size_32K to 
.l1dSize = CacheP_L1Size_16K in ti_dpl_config.c
- we are using SBL_QSPI which is executing only on RF5, what we need to change in the bootloader prior to rebuilding it to enable part of the L1D as SRAM and part as a cache? In the post above changing c66 related files, how that affects sbl_qspi which is not including c66 related nortos libraries? Could you provide similar change needed for arm related files?
Regards,
Predrag
  • 0
    TI__Expert 6130 points

    Hi Predrag,

    Can you share what all modifications you have done for your use case.

    Regards,

    Shruti

  • 0 in reply to shruti gupta
    Prodigy 10 points

    The changes done include:

    - change in ti_dpl_config.c file cache size for L1d to 16k from 32k

    - C:\ti\mmwave_mcuplus_sdk_04_04_01_02\mcu_plus_sdk_awr294x_09_00_00_15\source\kernel\.meta\dpl\cache_c6x.c.xdt change here also to .l1dSize = CacheP_L1Size_16K in gCacheSize prior to rebuliding sbl_multicore_app

    - other changes to linker and source code should not be an issue, this is part from the c66_linker.cmd:

    DSS_L1D:  ORIGIN = 0xF00000, LENGTH = 0x4000 (cache should be allocated from last address so I allocated first 16kB for L1D in SRAM)

    Additional question: SBL_QSPI.release.tiiimage, from which source folder is this generated sbl_qspi (rf5 only) or sbl_multicore_app(dsp + rf5).

    Problem I am getting after these changes is that when running in CCS DSS project it automatically stalls when code is downloaded to it.

    So to summarize:

    1) What changes are needed to be done in SBL source prior to rebuilding it and which source folder is related to sbl_qspi.release.tiimage prebuild sbl binary?

    2) Is there any more app code changes besides ti_dpl_config.c?

  • 0 in reply to Predrag Bratic
    TI__Expert 6130 points

    Hi Predrag,

    Let me check this internally and get back to you.

    Regards,

    Shruti