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AWR1843AOPEVM: ADC raw data capture on Ubuntu using DCA1000

Part Number: AWR1843AOPEVM
Other Parts Discussed in Thread: AWR1843AOP, DCA1000EVM

Tool/software:

Hi TI,

We are working on DCA1000 and AWR1843AOP EVM for raw data collection. For our application,we have to work on ubuntu system, So  we decided to use DCA1000 CLI commands for raw data collection. In the DCA1000 CLI software user guide it is mentioned under system requirements for Linux systems as Ubuntu 16xx LTS 64-bit OS. In the ubuntu 20.04 version we connected the DCA1000 board and it is getting detected, but the drivers are coming as none. Please find the attached picture, in that under AR DEV pack ports are coming as none. Can you provide solution for this FTDI drivers?

Is it necessary to use ubuntu 16xx ? Can we use ubuntu 20.04 version? 


Thank you,

With regards,
Rashmika

  • Hey Rashmika,

    As a general comment, we unfortunately don't offer much support for Linux currently. We highly recommend developing on Windows if possible or using a Virtual Machine to operate within a Windows environment as most of our software packages have not been extensively tested on Linux distros.

    Since Ubuntu 11.10, the FTDI VCP drivers have been integrated into the kernel. The DCA1000 should use the FTDI VCP drivers, but you may also need the D2xx drivers as well which can be found at the link below.

    FTDI D2xx Drivers: https://ftdichip.com/drivers/d2xx-drivers/

    As for Ubuntu versions, you should be able to use Ubuntu 20.04.

    Let me know if you have any other questions.

    Regards,

    Kristien

  • Hi TI,

    On Ubuntu we are using DCA1000 CLI commands for adc raw data capture. we sorted the issue of drivers. We followed the steps which are provided in DCA1000_CLI software user guide. All the commands which we are sending are giving success except stop_record command as shown in the attached picture.when we are sending start record command the DATA_TRAN_PRG LED starts blinking. But after giving the stop command that led is still blinking.It is not switching off. We tried the troubleshooting steps which are given in software user guide i.e, manual kill process of record but it is not working. Also find the attached .json file which we are putting in the release folder.

     
    Please resolve this issue.

    {
      "DCA1000Config": {
        "dataLoggingMode": "raw",
        "dataTransferMode": "LVDSCapture",
        "dataCaptureMode": "ethernetStream",
        "lvdsMode": 2,
        "dataFormatMode": 3,
        "packetDelay_us": 25,
        "ethernetConfig": {
          "DCA1000IPAddress": "192.168.33.180",
          "DCA1000ConfigPort": 4096,
          "DCA1000DataPort": 4098
        },
        "ethernetConfigUpdate": {
          "systemIPAddress": "192.168.33.30",
          "DCA1000IPAddress": "192.168.33.180",
          "DCA1000MACAddress": "12.34.56.78.90.12",
          "DCA1000ConfigPort": 4096,
          "DCA1000DataPort": 4098
        },
        "captureConfig": {
          "fileBasePath": "/home/satyajit/ti/DCA1000/DCA1000/SourceCode",
          "filePrefix": "adc_data",
          "maxRecFileSize_MB": 1024,
          "sequenceNumberEnable": 1,
          "captureStopMode": "infinite",
          "bytesToCapture": 4000,
          "durationToCapture_ms": 10000,
          "framesToCapture": 40
        },
        "dataFormatConfig": {
          "MSBToggle": 0,
          "laneFmtMap": 0,
          "reorderEnable": 0,
          "dataPortConfig": [
            {
              "portIdx": 0,
              "dataType": "real"
            },
            {
              "portIdx": 1,
              "dataType": "complex"
            },
            {
              "portIdx": 2,
              "dataType": "real"
            },
            {
              "portIdx": 3,
              "dataType": "real"
            },
            {
              "portIdx": 4,
              "dataType": "complex"
            }
          ]
        }
      }
    }

  • Hey Rashmika,

    Let me reach out to another engineer who's worked more extensively with the DCA1000 CLI to see if they have any input. Give me a day or two to respond.

    Regards,

    Kristien

  • Okay Kristien. Please give answer as soon as possible.

  • Hey Rashmika,

    There should be a CLI_LogFile.txt that is generated by the CLI tool. Can you please post that to the thread, so that we can take a look?

    Regards,

    Kristien

  • HI, Rashmika:

    Is the ADC running in complex mode? Or real mode?  I believe the OOB demo only support complex1x mode.  

    On the json file I have, I have all port in complex mode:

    "dataPortConfig": [
    {
    "portIdx": 0,
    "dataType": "complex"
    },
    {
    "portIdx": 1,
    "dataType": "complex"
    },
    {
    "portIdx": 2,
    "dataType": "complex"
    },
    {
    "portIdx": 3,
    "dataType": "complex"
    },
    {
    "portIdx": 4,
    "dataType": "complex"
    }
    ]

    Best,

    Zigang

  • Hi Kristien,

    Please find the attached CLI_LogFile.txt.

    0068.CLI_LogFile.txt
    Tue Nov  5 12:37:58 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 12:38:08 2024
    FPGA Configuration : 
    OS error - -2
    
    Tue Nov  5 12:38:08 2024
    Return status : -2
    
    Tue Nov  5 12:43:37 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 12:43:47 2024
    FPGA Configuration : 
    OS error - -2
    
    Tue Nov  5 12:43:47 2024
    Return status : -2
    
    Tue Nov  5 12:45:01 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 12:45:01 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 12:45:01 2024
    Return status : 0
    
    Tue Nov  5 12:45:28 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 12:45:28 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 12:45:28 2024
    Return status : 0
    
    Tue Nov  5 12:46:38 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 12:46:38 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 12:46:38 2024
    Return status : 0
    
    Tue Nov  5 12:46:54 2024
    Start Record Command (req)
    
    Tue Nov  5 12:46:54 2024
    Start Record command : Success
    
    Tue Nov  5 12:46:54 2024
    Return status : 0
    
    Tue Nov  5 12:46:59 2024
    Record is completed
    
    Tue Nov  5 12:47:46 2024
    stop_record
    
    Tue Nov  5 12:47:46 2024
    Stop the already running process.
    
    Tue Nov  5 12:47:54 2024
    stop_record
    
    Tue Nov  5 12:47:54 2024
    Stop the already running process.
    
    Tue Nov  5 12:48:50 2024
    reset_fpga
    
    Tue Nov  5 12:48:50 2024
    Stop the already running process.
    
    Tue Nov  5 12:49:21 2024
    Stop Record Command (req)
    
    Tue Nov  5 12:49:28 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Tue Nov  5 12:49:36 2024
    stop_record
    
    Tue Nov  5 12:49:36 2024
    No record process is running.
    
    Tue Nov  5 12:49:47 2024
    Reset FPGA Command (req)
    
    Tue Nov  5 12:49:47 2024
    Reset FPGA command : Success
    
    Tue Nov  5 12:49:47 2024
    Return status : 0
    
    Tue Nov  5 14:23:58 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 14:23:58 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 14:23:58 2024
    Return status : 0
    
    Tue Nov  5 14:25:45 2024
    Configure Record Command (req)
    
    Tue Nov  5 14:25:45 2024
    Configure Record command : Success
    
    Tue Nov  5 14:25:45 2024
    Return status : 0
    
    Tue Nov  5 14:26:24 2024
    Start Record Command (req)
    
    Tue Nov  5 14:26:24 2024
    Start Record Command (req)
    
    Tue Nov  5 14:26:24 2024
    Start Record command : Success
    
    Tue Nov  5 14:26:24 2024
    Start Record command : Success
    
    Tue Nov  5 14:26:24 2024
    Return status : 0
    
    Tue Nov  5 14:26:40 2024
    Stop Record Command (req)
    
    Tue Nov  5 14:26:47 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Tue Nov  5 14:28:34 2024
    stop_record
    
    Tue Nov  5 14:28:34 2024
    No record process is running.
    
    Tue Nov  5 14:29:02 2024
    stop_record
    
    Tue Nov  5 14:29:02 2024
    No record process is running.
    
    Tue Nov  5 14:34:37 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 14:34:37 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 14:34:37 2024
    Return status : 0
    
    Tue Nov  5 14:34:48 2024
    Configure Record Command (req)
    
    Tue Nov  5 14:34:48 2024
    Configure Record command : Success
    
    Tue Nov  5 14:34:48 2024
    Return status : 0
    
    Tue Nov  5 14:35:03 2024
    Start Record Command (req)
    
    Tue Nov  5 14:35:03 2024
    Start Record Command (req)
    
    Tue Nov  5 14:35:03 2024
    Start Record command : Success
    
    Tue Nov  5 14:35:03 2024
    Start Record command : Success
    
    Tue Nov  5 14:35:03 2024
    Return status : 0
    
    Tue Nov  5 14:36:04 2024
    Stop Record Command (req)
    
    Tue Nov  5 14:36:12 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Tue Nov  5 14:45:04 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 14:45:04 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 14:45:04 2024
    Return status : 0
    
    Tue Nov  5 14:45:43 2024
    Configure Record Command (req)
    
    Tue Nov  5 14:45:43 2024
    Configure Record command : Success
    
    Tue Nov  5 14:45:43 2024
    Return status : 0
    
    Tue Nov  5 14:55:15 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 14:55:15 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 14:55:15 2024
    Return status : 0
    
    Tue Nov  5 14:55:33 2024
    Configure Record Command (req)
    
    Tue Nov  5 14:55:33 2024
    Configure Record command : Success
    
    Tue Nov  5 14:55:33 2024
    Return status : 0
    
    Tue Nov  5 14:58:35 2024
    stop_record
    
    Tue Nov  5 14:58:35 2024
    No record process is running.
    
    Tue Nov  5 14:58:52 2024
    Start Record Command (req)
    
    Tue Nov  5 14:58:52 2024
    Start Record Command (req)
    
    Tue Nov  5 14:58:52 2024
    Start Record command : Success
    
    Tue Nov  5 14:58:52 2024
    Start Record command : Success
    
    Tue Nov  5 14:58:52 2024
    Return status : 0
    
    Tue Nov  5 14:59:03 2024
    Stop Record Command (req)
    
    Tue Nov  5 14:59:10 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Tue Nov  5 15:20:11 2024
    Ethernet connection
    
    Tue Nov  5 15:20:11 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 15:20:51 2024
    Ethernet connection
    
    Tue Nov  5 15:20:51 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 15:21:27 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 15:21:27 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 15:21:27 2024
    Return status : 0
    
    Tue Nov  5 15:21:38 2024
    Configure Record Command (req)
    
    Tue Nov  5 15:21:38 2024
    Configure Record command : Success
    
    Tue Nov  5 15:21:38 2024
    Return status : 0
    
    Tue Nov  5 15:21:45 2024
    Start Record Command (req)
    
    Tue Nov  5 15:21:46 2024
    Start Record Command (req)
    
    Tue Nov  5 15:21:46 2024
    Start Record command : Success
    
    Tue Nov  5 15:21:46 2024
    Start Record command : Success
    
    Tue Nov  5 15:21:46 2024
    Return status : 0
    
    Tue Nov  5 15:21:55 2024
    Stop Record Command (req)
    
    Tue Nov  5 15:22:03 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Tue Nov  5 17:03:10 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 17:03:20 2024
    FPGA Configuration : 
    OS error - -2
    
    Tue Nov  5 17:03:20 2024
    Return status : -2
    
    Tue Nov  5 17:03:36 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 17:03:36 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 17:03:36 2024
    Return status : 0
    
    Tue Nov  5 17:04:01 2024
    Configure Record Command (req)
    
    Tue Nov  5 17:04:01 2024
    Configure Record command : Success
    
    Tue Nov  5 17:04:01 2024
    Return status : 0
    
    Tue Nov  5 17:04:11 2024
    Start Record Command (req)
    
    Tue Nov  5 17:04:11 2024
    Start Record Command (req)
    
    Tue Nov  5 17:04:11 2024
    Start Record command : Success
    
    Tue Nov  5 17:04:11 2024
    Start Record command : Success
    
    Tue Nov  5 17:04:11 2024
    Return status : 0
    
    Tue Nov  5 17:04:21 2024
    Stop Record Command (req)
    
    Tue Nov  5 17:04:29 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Tue Nov  5 17:04:32 2024
    stop_record
    
    Tue Nov  5 17:04:32 2024
    No record process is running.
    
    Tue Nov  5 17:04:43 2024
    Ethernet connection
    
    Tue Nov  5 17:04:43 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:04:50 2024
    Ethernet connection
    
    Tue Nov  5 17:04:50 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:05:05 2024
    stop_record
    
    Tue Nov  5 17:05:05 2024
    No record process is running.
    
    Tue Nov  5 17:05:25 2024
    stop_record
    
    Tue Nov  5 17:05:25 2024
    No record process is running.
    
    Tue Nov  5 17:08:15 2024
    Ethernet connection
    
    Tue Nov  5 17:08:15 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:08:18 2024
    Ethernet connection
    
    Tue Nov  5 17:08:18 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:08:37 2024
    Ethernet connection
    
    Tue Nov  5 17:08:37 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:08:45 2024
    Ethernet connection
    
    Tue Nov  5 17:08:45 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:09:11 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 17:09:11 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 17:09:11 2024
    Return status : 0
    
    Tue Nov  5 17:09:33 2024
    Start Record Command (req)
    
    Tue Nov  5 17:09:33 2024
    Start Record Command (req)
    
    Tue Nov  5 17:09:33 2024
    Start Record command : Success
    
    Tue Nov  5 17:09:33 2024
    Start Record command : Success
    
    Tue Nov  5 17:09:33 2024
    Return status : 0
    
    Tue Nov  5 17:09:39 2024
    Stop Record Command (req)
    
    Tue Nov  5 17:09:47 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Tue Nov  5 17:09:48 2024
    stop_record
    
    Tue Nov  5 17:09:48 2024
    No record process is running.
    
    Tue Nov  5 17:09:49 2024
    stop_record
    
    Tue Nov  5 17:09:49 2024
    No record process is running.
    
    Tue Nov  5 17:09:50 2024
    stop_record
    
    Tue Nov  5 17:09:50 2024
    No record process is running.
    
    Tue Nov  5 17:10:16 2024
    Ethernet connection
    
    Tue Nov  5 17:10:16 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:10:27 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 17:10:27 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 17:10:27 2024
    Return status : 0
    
    Tue Nov  5 17:10:43 2024
    Start Record Command (req)
    
    Tue Nov  5 17:10:43 2024
    Start Record Command (req)
    
    Tue Nov  5 17:10:43 2024
    Start Record command : Success
    
    Tue Nov  5 17:10:43 2024
    Start Record command : Success
    
    Tue Nov  5 17:10:43 2024
    Return status : 0
    
    Tue Nov  5 17:10:48 2024
    Stop Record Command (req)
    
    Tue Nov  5 17:10:55 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Tue Nov  5 17:11:00 2024
    stop_record
    
    Tue Nov  5 17:11:00 2024
    No record process is running.
    
    Tue Nov  5 17:11:01 2024
    stop_record
    
    Tue Nov  5 17:11:01 2024
    No record process is running.
    
    Tue Nov  5 17:11:02 2024
    stop_record
    
    Tue Nov  5 17:11:02 2024
    No record process is running.
    
    Tue Nov  5 17:18:58 2024
    stop_record
    
    Tue Nov  5 17:18:58 2024
    No record process is running.
    
    Tue Nov  5 17:25:13 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 17:25:13 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 17:25:13 2024
    Return status : 0
    
    Tue Nov  5 17:25:24 2024
    Configure Record Command (req)
    
    Tue Nov  5 17:25:24 2024
    Configure Record command : Success
    
    Tue Nov  5 17:25:24 2024
    Return status : 0
    
    Tue Nov  5 17:25:32 2024
    Start Record Command (req)
    
    Tue Nov  5 17:25:33 2024
    Start Record Command (req)
    
    Tue Nov  5 17:25:33 2024
    Start Record command : Success
    
    Tue Nov  5 17:25:33 2024
    Start Record command : Success
    
    Tue Nov  5 17:25:33 2024
    Return status : 0
    
    Tue Nov  5 17:25:42 2024
    Stop Record Command (req)
    
    Tue Nov  5 17:25:49 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Tue Nov  5 17:44:45 2024
    Ethernet connection
    
    Tue Nov  5 17:44:45 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:44:53 2024
    Ethernet connection
    
    Tue Nov  5 17:44:53 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:45:01 2024
    Ethernet connection
    
    Tue Nov  5 17:45:01 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:45:10 2024
    Ethernet connection
    
    Tue Nov  5 17:45:10 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:45:28 2024
    Ethernet connection
    
    Tue Nov  5 17:45:28 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:45:47 2024
    Ethernet connection
    
    Tue Nov  5 17:45:47 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:46:48 2024
    Ethernet connection
    
    Tue Nov  5 17:46:48 2024
    Ethernet connection failed. [error -4051]
    
    Tue Nov  5 17:47:06 2024
    FPGA Configuration Command (req)
    
    Tue Nov  5 17:47:06 2024
    FPGA Configuration command : Success
    
    Tue Nov  5 17:47:06 2024
    Return status : 0
    
    Tue Nov  5 17:47:14 2024
    Configure Record Command (req)
    
    Tue Nov  5 17:47:14 2024
    Configure Record command : Success
    
    Tue Nov  5 17:47:14 2024
    Return status : 0
    
    Tue Nov  5 17:47:23 2024
    Start Record Command (req)
    
    Tue Nov  5 17:47:23 2024
    Start Record Command (req)
    
    Tue Nov  5 17:47:23 2024
    Start Record command : Success
    
    Tue Nov  5 17:47:24 2024
    Start Record command : Success
    
    Tue Nov  5 17:47:24 2024
    Return status : 0
    
    Tue Nov  5 17:47:43 2024
    Stop Record Command (req)
    
    Tue Nov  5 17:47:51 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Wed Nov  6 11:02:37 2024
    Ethernet connection
    
    Wed Nov  6 11:02:37 2024
    Ethernet connection failed. [error -4051]
    
    Wed Nov  6 11:02:49 2024
    Ethernet connection
    
    Wed Nov  6 11:02:49 2024
    Ethernet connection failed. [error -4051]
    
    Wed Nov  6 11:03:19 2024
    Ethernet connection
    
    Wed Nov  6 11:03:19 2024
    Ethernet connection failed. [error -4051]
    
    Wed Nov  6 11:04:00 2024
    FPGA Configuration Command (req)
    
    Wed Nov  6 11:04:00 2024
    FPGA Configuration command : Success
    
    Wed Nov  6 11:04:00 2024
    Return status : 0
    
    Wed Nov  6 11:04:09 2024
    Configure Record Command (req)
    
    Wed Nov  6 11:04:09 2024
    Configure Record command : Success
    
    Wed Nov  6 11:04:09 2024
    Return status : 0
    
    Wed Nov  6 11:04:15 2024
    Start Record Command (req)
    
    Wed Nov  6 11:04:16 2024
    Start Record Command (req)
    
    Wed Nov  6 11:04:16 2024
    Start Record command : Success
    
    Wed Nov  6 11:04:16 2024
    Start Record command : Success
    
    Wed Nov  6 11:04:16 2024
    Return status : 0
    
    Wed Nov  6 11:04:27 2024
    Stop Record Command (req)
    
    Wed Nov  6 11:04:35 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Wed Nov  6 11:06:25 2024
    stop_record
    
    Wed Nov  6 11:06:25 2024
    No record process is running.
    
    Wed Nov  6 11:07:02 2024
    FPGA Configuration Command (req)
    
    Wed Nov  6 11:07:02 2024
    FPGA Configuration command : Success
    
    Wed Nov  6 11:07:02 2024
    Return status : 0
    
    Wed Nov  6 11:07:10 2024
    Configure Record Command (req)
    
    Wed Nov  6 11:07:10 2024
    Configure Record command : Success
    
    Wed Nov  6 11:07:10 2024
    Return status : 0
    
    Wed Nov  6 11:07:18 2024
    Start Record Command (req)
    
    Wed Nov  6 11:07:18 2024
    Start Record Command (req)
    
    Wed Nov  6 11:07:18 2024
    Start Record command : Success
    
    Wed Nov  6 11:07:18 2024
    Start Record command : Success
    
    Wed Nov  6 11:07:18 2024
    Return status : 0
    
    Wed Nov  6 11:08:06 2024
    fpga
    
    Wed Nov  6 11:08:06 2024
    Stop the already running process.
    
    Wed Nov  6 11:08:22 2024
    fpga
    
    Wed Nov  6 11:08:22 2024
    Stop the already running process.
    
    Wed Nov  6 11:09:12 2024
    fpga
    
    Wed Nov  6 11:09:12 2024
    Stop the already running process.
    
    Wed Nov  6 11:09:57 2024
    fpga
    
    Wed Nov  6 11:09:57 2024
    Stop the already running process.
    
    Wed Nov  6 11:11:12 2024
    fpga
    
    Wed Nov  6 11:11:12 2024
    Stop the already running process.
    
    Wed Nov  6 11:11:34 2024
    Stop Record Command (req)
    
    Wed Nov  6 11:11:42 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Wed Nov  6 11:15:24 2024
    FPGA Configuration Command (req)
    
    Wed Nov  6 11:15:24 2024
    FPGA Configuration command : Success
    
    Wed Nov  6 11:15:24 2024
    Return status : 0
    
    Wed Nov  6 11:15:49 2024
    Configure Record Command (req)
    
    Wed Nov  6 11:15:49 2024
    Configure Record command : Success
    
    Wed Nov  6 11:15:49 2024
    Return status : 0
    
    Wed Nov  6 11:16:09 2024
    Start Record Command (req)
    
    Wed Nov  6 11:16:09 2024
    Start Record Command (req)
    
    Wed Nov  6 11:16:09 2024
    Start Record command : Success
    
    Wed Nov  6 11:16:09 2024
    Start Record command : Success
    
    Wed Nov  6 11:16:09 2024
    Return status : 0
    
    Wed Nov  6 11:17:10 2024
    Stop Record Command (req)
    
    Wed Nov  6 11:17:17 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Wed Nov  6 11:17:33 2024
    stop_record
    
    Wed Nov  6 11:17:33 2024
    No record process is running.
    
    Wed Nov  6 11:18:11 2024
    FPGA Configuration Command (req)
    
    Wed Nov  6 11:18:11 2024
    FPGA Configuration command : Success
    
    Wed Nov  6 11:18:11 2024
    Return status : 0
    
    Wed Nov  6 11:18:20 2024
    Configure Record Command (req)
    
    Wed Nov  6 11:18:20 2024
    Configure Record command : Success
    
    Wed Nov  6 11:18:20 2024
    Return status : 0
    
    Wed Nov  6 11:18:27 2024
    Start Record Command (req)
    
    Wed Nov  6 11:18:28 2024
    Start Record Command (req)
    
    Wed Nov  6 11:18:28 2024
    Start Record command : Success
    
    Wed Nov  6 11:18:28 2024
    Start Record command : Success
    
    Wed Nov  6 11:18:28 2024
    Return status : 0
    
    Wed Nov  6 11:20:00 2024
    Stop Record Command (req)
    
    Wed Nov  6 11:20:08 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Wed Nov  6 11:20:20 2024
    FPGA Configuration Command (req)
    
    Wed Nov  6 11:20:20 2024
    FPGA Configuration command : Success
    
    Wed Nov  6 11:20:20 2024
    Return status : 0
    
    Wed Nov  6 11:52:52 2024
    FPGA Configuration Command (req)
    
    Wed Nov  6 11:52:52 2024
    FPGA Configuration command : Success
    
    Wed Nov  6 11:52:52 2024
    Return status : 0
    
    Wed Nov  6 11:53:02 2024
    Configure Record Command (req)
    
    Wed Nov  6 11:53:02 2024
    Configure Record command : Success
    
    Wed Nov  6 11:53:02 2024
    Return status : 0
    
    Wed Nov  6 11:53:11 2024
    Start Record Command (req)
    
    Wed Nov  6 11:53:12 2024
    Start Record Command (req)
    
    Wed Nov  6 11:53:12 2024
    Start Record command : Success
    
    Wed Nov  6 11:53:12 2024
    Start Record command : Success
    
    Wed Nov  6 11:53:12 2024
    Return status : 0
    
    Wed Nov  6 11:56:38 2024
    Stop Record Command (req)
    
    Wed Nov  6 11:56:45 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Wed Nov  6 14:00:30 2024
    FPGA Configuration Command (req)
    
    Wed Nov  6 14:00:30 2024
    FPGA Configuration command : Success
    
    Wed Nov  6 14:00:30 2024
    Return status : 0
    
    Wed Nov  6 14:00:43 2024
    Configure Record Command (req)
    
    Wed Nov  6 14:00:43 2024
    Configure Record command : Success
    
    Wed Nov  6 14:00:43 2024
    Return status : 0
    
    Wed Nov  6 14:01:11 2024
    Start Record Command (req)
    
    Wed Nov  6 14:01:12 2024
    Start Record Command (req)
    
    Wed Nov  6 14:01:12 2024
    Start Record command : Success
    
    Wed Nov  6 14:01:12 2024
    Start Record command : Success
    
    Wed Nov  6 14:01:12 2024
    Return status : 0
    
    Wed Nov  6 14:02:13 2024
    Stop Record Command (req)
    
    Wed Nov  6 14:02:21 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Thu Nov  7 09:51:49 2024
    FPGA Configuration Command (req)
    
    Thu Nov  7 09:51:50 2024
    FPGA Configuration command : Success
    
    Thu Nov  7 09:51:50 2024
    Return status : 0
    
    Thu Nov  7 09:52:00 2024
    Configure Record Command (req)
    
    Thu Nov  7 09:52:00 2024
    Configure Record command : Success
    
    Thu Nov  7 09:52:00 2024
    Return status : 0
    
    Thu Nov  7 09:52:30 2024
    Start Record Command (req)
    
    Thu Nov  7 09:52:31 2024
    Start Record Command (req)
    
    Thu Nov  7 09:52:31 2024
    Start Record command : Success
    
    Thu Nov  7 09:52:31 2024
    Start Record command : Success
    
    Thu Nov  7 09:52:31 2024
    Return status : 0
    
    Thu Nov  7 09:53:13 2024
    Stop Record Command (req)
    
    Thu Nov  7 09:53:20 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    
    Thu Nov  7 09:54:42 2024
    FPGA Configuration Command (req)
    
    Thu Nov  7 09:54:42 2024
    FPGA Configuration command : Success
    
    Thu Nov  7 09:54:42 2024
    Return status : 0
    
    Thu Nov  7 09:54:51 2024
    Configure Record Command (req)
    
    Thu Nov  7 09:54:51 2024
    Configure Record command : Success
    
    Thu Nov  7 09:54:51 2024
    Return status : 0
    
    Thu Nov  7 09:55:04 2024
    Start Record Command (req)
    
    Thu Nov  7 09:55:04 2024
    Start Record Command (req)
    
    Thu Nov  7 09:55:04 2024
    Start Record command : Success
    
    Thu Nov  7 09:55:04 2024
    Start Record command : Success
    
    Thu Nov  7 09:55:04 2024
    Return status : 0
    
    Thu Nov  7 09:55:13 2024
    Stop Record Command (req)
    
    Thu Nov  7 09:55:21 2024
    Stop Record command : Timeout Error! Couldnt read the record process status. [error -4068]
    


    With regards,

    Rashmika

  • Hey Rashmika,

    Give me a day to look over your file.

    Regards,

    Kristien

  • Hi Zigang,

    Yes, it is running in complex1x mode. I tried it using the json file with all complex values for all portIdx's. But it didn't resolve.


  • Hi Kristien,

    Please give reply as soon as possible.

    Regards,

    Rashmika

  • Hey Rashmika,

    You can attempt to increase the timeout for the connection in the cli_control_main.cpp by changing the CLI_CMD_TIMEOUT_DURATION macro defined in the globals.h file and recompiling the source code. By default, the timeout is around 7 seconds which does appear to match the log timestamps. 

    I believe you may be able to debug the program using the GNU project debugger. Stepping through the IsRecordProcStopped and QueryRecordProcStatus function would help us understand further why stop_record appears to be failing.

    Regards,

    Kristien

  • Hi TI,

    We installed wine on ubuntu system using 

    sudo apt update 

    sudo apt install wine 64

    then we copied related dll files and .exe files from windows to ubuntu. Please find the files in the attached screenshot.

    Then we gave commands same as windows. The format is as shown below:

    wine DCA1000EVM_CLI_control.exe fpga cf.json

    Then it started recording and was able to stop successfully by generating the .bin file. 


  • Hey Rashmika,

    Thank you for the update. To confirm, it sounds like you were able to resolve this issue by using Wine to run the program, correct? If so, we can close out the thread.

    Regards,

    Kristien

  • Hi TI,

    Yes, it got resolved using Wine. But the generated bin file is adc_data_Raw_0.bin which has to pass through Packet_Reorder_Zerofill.exe to remove the packet header, packet sequence number and to put in an order. This Packet_Reorder_Zerofill.exe is not working on ubuntu with wine also. Please find the attached screenshot of error while running Packet_Reorder_Zerofill.exe on ubuntu with wine.




    Thank you,

    With Regards,
    Rashmika

  • Hey Rashmika,

    Thank you for letting us know about this issue. As stated under Section 3.3 of the mmWaveStudio User Guide, the packet reorder utility should not be needed before post-processing as the data should already be reordered and ready for post processing. Let me know if you have any other issues.

    Regards,

    Kristien

  • Hi TI,

    We are not using mmWaveStudio for data collection. We are using DCA1000 CLI commands for collecting the raw data. We compared the same scenario data of mmWave studio and DCA1000 CLI commands. mmWave studio generated the adc_data.bin file whereas DCA1000 CLI commands method generated the adc_data_Raw_0.bin file. We compared the two bin files in MATLAB through post processing. It generated different results. 

    So, after going through the documents we came to know that in mmWave studio Packet_Reorder_Zerofill.exe is performed automatically. But in the DCA1000 CLI commands it is not happening. So, please suggest the command to pass the generated bin file of DCA1000 CLI commands through Packet_Reorder_Zerofill.exe. 

    Please resolve the issue as soon as possible.

    Thank you,

    With Regards,
    Rashmika Thota

  • Hey Rashmika,

    I apologize for not catching the distinction between mmWaveStudio and the DCA1000 CLI commands. While I would like to support you further, we recently released a DCA1000 FAQ in which we state that we will not support questions regarding configuring, starting, and recording data from the DCA1000 using the command line alone, and that we don't officially support operating systems outside of Windows. Please review the linked FAQ for more details.

    e2e.ti.com/.../faq-dca1000evm-support-tools-debugging-and-more

    I understand that there are may be some reasons that Linux is needed for your development environment, but please understand that Windows is all we can support currently. If you are able to resolve this issue on your own, I would highly recommend replying to this thread for other Linux users who may also be running into the same issues here. Otherwise, we will automatically close out this thread within 30 days of no activity.

    Thank you,

    Kristien