IWR6843AOP: Query on Sensing Performance and Simulation for IWR6843AOP in Custom PCB Design

Hi Dileep,

Please find below my responses:

1.  

Dileep Sharma said:

When designing the mmWave radar's PCB for our product, our initial approach is to replicate the evaluation board's design IWR6843AOPEVM on our PCB to minimize any deviations or influences caused by design changes. However, if space constraints arise—such as positioning the mmWave radar IC (IWR6843AOP) at the center of the product what impact could this positional change (e.g., moving the IC IWR6843AOP to the center or corner relative to the evaluation board design) have on the radar's sensing performance?

Please refer to the IWR6843AOP device errata advisory number PACKAGE#02: Surface Wave Artefact from PCB, for guidelines about device placement.

IWR6843AOP Device Silicon Errata 

2.

Dileep Sharma said:

Is there a method to simulate the IWR6843AOP module's sensing performance within the product's enclosure to evaluate potential impacts?

If TI EVM is followed there won't be necessity for simulations. If you still want them, please contact your local TI field team. The simulation information is available for NDA signed customers.

3. 

Dileep Sharma said:

what are the possible most compulsory test we need to perform at the production line for the mmWave radar IWR6843AOPEVM.

Please refer to mmWave Production Testing Overview application note for this query.

4. 

Dileep Sharma said:

ETSI EN 305-550-1 suggested on your website states that device “Must be able to turn off the radar if other radar devices are nearby”. Is this feature available in TI’s RADAR chip? (dev.ti.com/.../node

Yes, this feature is available in TI's radar devices.

5.

Dileep Sharma said:

Is 60GHz-64GHz frequency band allowed in India and UK for in-house commercial use applications?

In India, the regulatory guidelines keep changing. It would be best to contact local regulatory test houses to get the most recent regulations.

For UK too, the regulations keep changing especially after the Brexit happened. Hence it would be best for UK also to contact the local test houses to get the most recent regulations.

6.

Dileep Sharma said:

is there any way to simulate IWR6843AOP antenna performance? 

Yes, there is. Please contact your local TI field team for more details on it. The simulation information is available for NDA signed customers.

Thanks

Swarnendu

Dileep,

The best document to refer to get guidance on the hardware design is the hardware design checklist: https://www.ti.com/lit/zip/swrr197 

It has all the necessary information for hardware design. Please refer to different sections in the checklist. 

Thanks,

Swarnendu

Hi Dileep,

Bandwidth does not have direct impact over the max range, max velocity, velocity resolution, angular range or angular resolution. Field of view also depends on the antenna radiation pattern and is unaffected by chirp bandwidth.

However, it has impact over the range resolution. With 500MHz bandwidth, the range resolution will be 30cm. Hence, it will also have some impact on static presence detection and people counting/tracking. If multiple objects stay less than 30cm apart, they will be considered as a single object.

For a better understanding on the chirp parameters and their impact over radar performance, I would like to refer to the application note to you: 

https://www.ti.com/lit/an/swra553a/swra553a.pdf (link)

Please take a look on the appnote for other detailed considerations.

Thanks,

Swarnendu

Hi Dileep,

I am doing well. Hope you too are doing fine.

It is OKAY to put the AOP device close to the PCB edge on one side. In that case I would recommend having the trapezoidal cut out on the other side of the PCB. I assume the device will not have PCB edges in both the north and south sides. If cut out or PCB edge is not placed in both the sides, ripples could be observed in the antenna radiation pattern in the elevation side as depicted in the device errata.

For radome design, please refer to the below appnote:

https://www.ti.com/lit/an/swra705/swra705.pdf 

Longer components should not be placed in the device side of the PCB. 

Thanks,

Swarnendu.

Dileep,

I would recommend you stick with the provided dimensions in errata for the trapezoidal cut:

These dimensions are optimized through antenna simulations. Also, I would like to recommend the device to PCB edge distance be less than or equal to 0.3mm. This is to prevent higher order radiations as well as to prevent unwanted emissions from other PCB components affecting the antenna performance. The design you provided with one side of the device facing the PCB edge and the other having the trapezoidal cut is alright, given the cut dimensions and the device to PCB edge distances are same as what is provided in the errata.

As an alternate workaround, as you asked, I can suggest using board to board connection. In this, the AOP device can be placed on a different board maintaining the edge to device spacings and taking out important signals out of the board to connect to the main board with other functionalities. This will help addressing area constraints.

However, the proposed design would work fine (i.e. PCB edge at one side and trapezoidal cut out at another).

With the recommended design, we should be able to address the surface wave artifacts. Regarding the antenna field of view, the north and south sides are anyway having no components. Considering the east and west sides, I would like to recommend placing components at least one wavelength away from the device. It is best if we can manage all other components to the other side of the PCB, but a one wavelength space is also fine.

Thanks,

Swarnendu

Hi Dileep,

From the diagram you shared, I can see the radar device placed on a narrow PCB that is allowing the radar device having PCB edges in both North and South sides. I would like to ensure that device edge to PCB edge space is <= 0.3mm. Also, is this a different PCB, as based on the previous discussions we came to a point that one side the device will have PCB edge and the other side a trapezoidal cut?

As far as I can see, the heat sink is below the radar device and not intersecting the radar device plane. In that case it is okay. Even though I would like to ensure that no component should come inside the RADAR FoV.

For the second question, yes there could be non-conducting material. The idea of introducing a trapezoidal cut is to ensure that at least in the marked area, there should not be any PCB to provide conducting surface so that it would interact with the radar performance. Again, I would like to sensitize that any components placed in the vicinity of radar device should not affect its FoV, hence the height of these components need to be checked properly.

Thanks,

Swarnendu

Dileep,

For the enclosure/radome design you can take a look at the below application note:

https://www.ti.com/lit/an/swra705/swra705.pdf 

Yes, as the heat sink lies below the device plane, it should not impact radar performance.

Also, integrating Wi-Fi should not interfere with the radar performance.

Thanks,

Swarnendu. 

Hi Dileep,

I would like to refer the below documentations for the antenna radiation patterns:

IWR6843AOP 

https://www.ti.com/lit/ds/symlink/iwr6843aop.pdf (Device data sheet - Section: RF Specification)

Regarding the surface wave artifacts, the optimized workarounds are mentioned in the device errata. Those should be well enough to deal with the same.

FoV is determined based on the antenna radiation pattern. The considerations are keeping the radar device at center. In both azimuth and elevation sides, the field of view is -60 deg to +60 deg.

Thanks,

Swarnendu

Hi Dileep,

1. The operation of each individual subsystems such as DSP/Processing highly depends on device configurations especially sampling rate, #Chirps, duty cycle etc. Hence it is difficult to standardize power dissipation for each of these subsystems.

2. Please refer to the application note: Thermal Design Guide for Antenna on Package mmWave Sensor (https://www.ti.com/lit/an/swra672/swra672.pdf)

You can use below function or API – to read the junction temperature.

mmwaveLink_getTemperatureReport()  

rlRfGetTemperatureReport()

3. If junction temperature is maintained below 105 deg C, below is the power on hours for the mmWave device.

You can check using the other knobs to reduce the temperature (Such as duty-cycle, Heat-sink options etc).

There should not be performance impact for frequent power cycles. But in longer terms it might stress out the PDN.

Thanks,

Swarnendu

Dileep,

Please find below my responses:

1. We do not have any comprehensive power numbers for the device idle state (i.e. front end inactive) because this is highly user specific. It depends on how many communication interfaces are active, what are the supplies to the device etc. However, the digital leakage power can be expected to be ~20mW.

2. There are many configuration parameters that the average power dissipation depends on. Definition of max. duty cycle also varies based on different regulations. To give you an estimate I am providing below some numbers. However, these will not be exactly specific.

2.1 Only 1 TX, High duty cycle: 1.7W

2.2 Only 2 TX, High duty cycle: 1.9W

2.3 All 3 TX, High duty cycle: 2.2W

3. I am stating below the improvements you will observe if more #TXs are used:

a) The transmitted power will be more.

b) #Virtual antenna array will increase with each TX antenna by a multiplication of #RXs, which will increase the angular resolution.

c) The overall noise floor will reduce.

Similarly with lesser TXs you will observe some degradation on the said factors.

You can further explore IWR6843AOP low power modes in the below resources:

https://www.ti.com/lit/an/swra689/swra689.pdf?ts=1734701696344&ref_url=https%253A%252F%252Fwww.google.com%252F 

https://dev.ti.com/tirex/explore/node?node=A__ALuG45QtveCbcI.ZvVcCOw__com.ti.mmwave_industrial_toolbox__VLyFKFf__LATEST 

Thanks,

Swarnendu