AWRL6844: QSPI communication

#include "MonitorFeatures.h"
#include "..\UMI3\UMI3_Engine.h"
#include "..\UMI3\Monitor_Utils.h"

#include "DeviceOperations_AWRL6844QSPI.h"
#include "cslr_soc_baseaddress.h"
#include <string.h>
#include <qspi.h>
#include <ClockP.h>

#define RTIDWDCTRL  (*((volatile DWORD *) 0x50020090))
#define RTIWDSTATUS (*((volatile DWORD *) 0x50020098))
#define RTIDWDKEY   (*((volatile WORD *) 0x5002009C))

/////////////////////////////////////////////////////////////////////////////////////
////Device_Specific_Defines_And_Functions////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////

uint32_t g_qspiHandle = NULL;
QSPI_Params g_qspi_params;
QSPI_Object *object;

QSPI_Config gQspiConfig[];
QSPI_Attrs *gQSPIAttr;

EDMA_Config gEdmaConfig[];
uint32_t gQspiConfigNum = 1;
uint32_t gEdmaConfigNum = 1;

ClockP_Config gClockConfig;


CSL_app_cfg_qspiRegs *g_pQspiRegs = (CSL_app_cfg_qspiRegs *)CSL_APP_CFG_QSPI_U_BASE;

static void s_Qspi_waitIdle()
{
  /* Wait while QSPI is busy */
  uint32_t dwQspiStatusReg = CSL_REG32_RD(&g_pQspiRegs->SPI_STATUS);
  while ((dwQspiStatusReg & CSL_APP_CFG_QSPI_SPI_STATUS_BUSY_MASK) == CSL_QSPI_SPI_STATUS_REG_BUSY_BUSY)
    dwQspiStatusReg = CSL_REG32_RD(&g_pQspiRegs->SPI_STATUS);
}

static uint8_t s_getCmdRegCmdPins(bool bWrite, uint8_t byNumPins)
{
  /* Write supports 4-pin operations (data out on D0 - MOSI, data in on D1 - MISO) or 3-pin operations (data out/in
     on D0 - some sort of multiplexed SPI, so avoid for now) */
  if (bWrite)
    return CSL_QSPI_SPI_CMD_REG_CMD_FOUR_PIN_WRITE_SINGLE;

  /* Read supports 3, 4 or 6-pin operations (data read on 1, 2 or 4 input pins) */
  switch (byNumPins)
  {
  case 1: return CSL_QSPI_SPI_CMD_REG_CMD_FOUR_PIN_READ_SINGLE;
  case 2: return CSL_QSPI_SPI_CMD_REG_CMD_FOUR_PIN_READ_DUAL;
  case 4: return CSL_QSPI_SPI_CMD_REG_CMD_SIX_PIN_READ_QUAD;
  default: return CSL_QSPI_SPI_CMD_REG_CMD_FOUR_PIN_WRITE_SINGLE;
  }
}



void initClocks()
{ 

  APP_RCM_LOCK0_KICK0 = RCM_KICK0;
  APP_RCM_LOCK0_KICK1 = RCM_KICK1;
  
  APP_QSPI_CLKCTL_REG = 0x03334440; // DIVR 1, SRCSEL - fast clk, GATE 0 (enable clock)
  APP_RCM_LOCK0_KICK0 = RCM_KICK_LOCK;
  APP_RCM_LOCK0_KICK1 = RCM_KICK_LOCK;

}

void initGPIO()
{
  // Unclock pad config registers
  IOCFGKICK0_REG = IOCFGKICK0_KEY;
  IOCFGKICK1_REG = IOCFGKICK1_KEY;

  // Set pads to appropriate modes and allow hardware control
  PAD_CFG_QSPI_0_REG  &= ~(QSPI_MODE_MASK | IE_OVERRIDE_CTRL | OE_OVERRIDE_CTRL);
  PAD_CFG_QSPI_1_REG  &= ~(QSPI_MODE_MASK | IE_OVERRIDE_CTRL | OE_OVERRIDE_CTRL);
  PAD_CFG_QSPI_2_REG  &= ~(QSPI_MODE_MASK | IE_OVERRIDE_CTRL | OE_OVERRIDE_CTRL);
  PAD_CFG_QSPI_3_REG  &= ~(QSPI_MODE_MASK | IE_OVERRIDE_CTRL | OE_OVERRIDE_CTRL);
  PAD_CFG_QSPI_CLK_REG &= ~(QSPI_MODE_MASK | IE_OVERRIDE_CTRL | OE_OVERRIDE_CTRL);
  PAD_CFG_QQSPI_CS_REG &= ~(QSPI_MODE_MASK | IE_OVERRIDE_CTRL | OE_OVERRIDE_CTRL);
}


BOOL Device_Init(DWORD dwFlags)
{
  gQspiConfigNum = 1;
  uint32_t errcode;
  // Set CPU clock to 200 Mhz
  initClocks();
  // Configure QSPI pads
  initGPIO();
  
  /* Set the SPI idle mode and wait for it to be idle */
  g_pQspiRegs->SYSCONFIG = CSL_APP_CFG_QSPI_SYSCONFIG_IDLEMODE_NO_IDLE << CSL_APP_CFG_QSPI_SYSCONFIG_IDLEMODE_SHIFT;
  s_Qspi_waitIdle();

  g_pQspiRegs->SPI_DC = CSL_APP_CFG_QSPI_SPI_DC_CKP0_RESETVAL  ; /* Clock polarity: low when data not being transfered,
                                                                 Chip select polarity: active low
                                                                 Clock phase: data shifted out on falling clock polarity,
                                                                          in on rising edge
                                                                 Data delay: same cycle as CS goes active */

  /* Clear the interrupts and interrupt status */
  g_pQspiRegs->INTR_ENABLE_CLEAR |= CSL_APP_CFG_QSPI_INTR_ENABLE_SET_FIRQ_ENA_SET_MASK |
                                        CSL_APP_CFG_QSPI_INTR_ENABLE_SET_WIRQ_ENA_SET_MASK;
  g_pQspiRegs->INTR_STATUS_ENABLED_CLEAR |= CSL_APP_CFG_QSPI_INTR_STATUS_ENABLED_CLEAR_FIRQ_ENA_MASK |
                                            CSL_APP_CFG_QSPI_INTR_STATUS_ENABLED_CLEAR_WIRQ_ENA_MASK;

  g_pQspiRegs->SPI_SWITCH = CSL_APP_CFG_QSPI_SPI_SWITCH_RESETVAL; /* Disable memory mapped mode */

  /* Set QSPI data clock's divider and enable it */
  g_pQspiRegs->SPI_CLOCK_CNTRL = CSL_APP_CFG_QSPI_SPI_CLOCK_CNTRL_CLKEN_RESETVAL;
  g_pQspiRegs->SPI_CLOCK_CNTRL |= 0 << 0;
  g_pQspiRegs->SPI_CLOCK_CNTRL |= CSL_QSPI_SPI_CLOCK_CNTRL_REG_CLKEN_DCLOCK_ON
                                      << CSL_APP_CFG_QSPI_SPI_CLOCK_CNTRL_CLKEN_SHIFT;

  return TRUE;
}

void Device_Idle()
{

}

BOOL Device_Deinit(DWORD dwFlags)
{
  return TRUE;
}

/* 
 * Device_Scan function called from UMI monitor. 
 * dwNumBytes         : num of bytes to read + num of address bytes
 * dwFlags            : num of data pins to use when sending/receiving commands, address, data
 *                      check GetNumInstrPinsFromFlags(), GetNumAddrPinsFromFlags(), GetNumDataPinsFromFlags()
 * byNumAddressBytes  : num of address bytes    
 * byNumDummyClocks   : num of dummy clocks
 * dwBytesToRead      : num of bytes to read
 * byCMD              : command to send
 * pbyDataStream      : pointer, data to send
 * g_abyReadBuff      : pointer, read buffer
*/
BOOL Device_Scan(DWORD dwNumBytes, DWORD dwFlags, BYTE byNumAddressBytes, 
                 BYTE byNumDummyClocks, DWORD dwBytesToRead, BYTE byCMD,
                 BYTE * pbyDataStream, BYTE * pbyReadBuff)
{
  uint8_t byNumInstrPins = GetNumInstrPinsFromFlags(dwFlags);
  uint8_t byNumAddrPins  = GetNumAddrPinsFromFlags(dwFlags);
  uint8_t byNumDataPins  = GetNumDataPinsFromFlags(dwFlags);

  const uint8_t c_byWriteTransferBytePackSize = 16;
  const uint8_t c_byReadTransferBytePackSize  = 16;
  uint32_t      dwBytesToWrite                = dwNumBytes - byNumAddressBytes;

  /* Frame length determines for how many read/write words QSPI module will keep CS pulled low once the transmission
     starts. */
  uint32_t frameLength = 1 +                                              /* Command byte - always one byte */
                         (byNumAddressBytes + 3) / 4 +                    /* Can transfer 4 byte address at once */
                         (byNumDummyClocks + 127) / 128 +                 /* Up to 128 dummy clocks (bits) at once*/
                         dwBytesToRead / c_byReadTransferBytePackSize +   /* 16 byte packed reads */
                         dwBytesToRead % c_byReadTransferBytePackSize +   /* Per byte reads */
                         dwBytesToWrite / c_byWriteTransferBytePackSize + /* 16 byte packed writes */
                         dwBytesToWrite % c_byWriteTransferBytePackSize;  /* Per byte writes */

    
  g_pQspiRegs->SPI_SWITCH = ~(1 << 0); // Clear MMPT_S

  /* Send command to the flash - always as first instruction */
  uint32_t dwQSPIx_SPI_CMD = QSPI_CS0 << CSL_APP_CFG_QSPI_SPI_CMD_CSNUM_SHIFT |
                                 (8 - 1) << CSL_APP_CFG_QSPI_SPI_CMD_WLEN_SHIFT |
                                 s_getCmdRegCmdPins(true, byNumInstrPins) << CSL_APP_CFG_QSPI_SPI_CMD_CMD_SHIFT |
                                 (frameLength - 1) << CSL_APP_CFG_QSPI_SPI_CMD_FLEN_SHIFT;

  s_Qspi_waitIdle();
  //g_pQspiRegs->SPI_DC |= ((CSL_APP_CFG_QSPI_SPI_DC_CKP0_MAX << CSL_APP_CFG_QSPI_SPI_DC_CKP0_SHIFT) | (CSL_APP_CFG_QSPI_SPI_DC_CKPH0_MAX << CSL_APP_CFG_QSPI_SPI_DC_CKPH0_SHIFT)); 
  g_pQspiRegs->SPI_DATA = byCMD; __asm__("DMB"); /* Write command to data register */
  g_pQspiRegs->SPI_CMD  = dwQSPIx_SPI_CMD;   /* Process Tx command - command out */

  /* Send address bytes if any */
  if (byNumAddressBytes)
  {
    uint32_t dwAddress = GetAddressFromBuffer(pbyDataStream, byNumAddressBytes);
    pbyDataStream += byNumAddressBytes;

    dwQSPIx_SPI_CMD = QSPI_CS0 << CSL_APP_CFG_QSPI_SPI_CMD_CSNUM_SHIFT |
                          ((byNumAddressBytes * 8) - 1) << CSL_APP_CFG_QSPI_SPI_CMD_WLEN_SHIFT |
                          s_getCmdRegCmdPins(true, byNumAddrPins) << CSL_APP_CFG_QSPI_SPI_CMD_CMD_SHIFT |
                          (frameLength - 1) << CSL_APP_CFG_QSPI_SPI_CMD_FLEN_SHIFT;

    s_Qspi_waitIdle();
    g_pQspiRegs->SPI_DATA = dwAddress; __asm__("DMB"); /* Write address to data register */
    g_pQspiRegs->SPI_CMD  = dwQSPIx_SPI_CMD;       /* Process Tx command - address out */
  }

  /* Send dummy bytes if any */
  if (byNumDummyClocks > 0)
  {
    dwQSPIx_SPI_CMD = QSPI_CS0 << CSL_APP_CFG_QSPI_SPI_CMD_CSNUM_SHIFT |
                          s_getCmdRegCmdPins(true, byNumDataPins) << CSL_APP_CFG_QSPI_SPI_CMD_CMD_SHIFT |
                          (frameLength - 1) << CSL_APP_CFG_QSPI_SPI_CMD_FLEN_SHIFT;

    /* Keep data pins low when transferring dummy bytes */
    s_Qspi_waitIdle();
    g_pQspiRegs->SPI_DATA  = 0;
    g_pQspiRegs->SPI_DATA1 = 0;
    g_pQspiRegs->SPI_DATA2 = 0;
    g_pQspiRegs->SPI_DATA3 = 0;
    __asm__("DMB");

    /* Max 128 dummy clocks (bits) can be transferred at once */
    do
    {
      uint8_t byNumDummyClocksNow = byNumDummyClocks > 128 ? 128 : byNumDummyClocks;
      dwQSPIx_SPI_CMD &= ~CSL_APP_CFG_QSPI_SPI_CMD_WLEN_MASK;
      dwQSPIx_SPI_CMD |= byNumDummyClocksNow;

      s_Qspi_waitIdle();
      g_pQspiRegs->SPI_CMD = dwQSPIx_SPI_CMD; /* Process Tx command - dummy clocks */

      byNumDummyClocks -= byNumDummyClocksNow;
    } while (byNumDummyClocks);
  }

  if (dwBytesToRead)
  {
    /* Read data */
    /* Use 16 byte (128 bit) transmissions for faster speed */
    dwQSPIx_SPI_CMD = QSPI_CS0 << CSL_APP_CFG_QSPI_SPI_CMD_CSNUM_SHIFT |
                          ((c_byReadTransferBytePackSize * 8) - 1) << CSL_APP_CFG_QSPI_SPI_CMD_WLEN_SHIFT |
                          s_getCmdRegCmdPins(false, byNumDataPins) << CSL_APP_CFG_QSPI_SPI_CMD_CMD_SHIFT |
                          (frameLength - 1) << CSL_APP_CFG_QSPI_SPI_CMD_FLEN_SHIFT;

    uint32_t *pdwReadBuff = (uint32_t *)(((uint32_t)pbyReadBuff + 3) & 0xFFFFFFFC);
    s_Qspi_waitIdle();
    for (uint32_t i = dwBytesToRead / c_byReadTransferBytePackSize; i > 0; i--)
    {
      g_pQspiRegs->SPI_CMD = dwQSPIx_SPI_CMD;
      s_Qspi_waitIdle();

      *pdwReadBuff++ = swap_DWORD(g_pQspiRegs->SPI_DATA3);
      *pdwReadBuff++ = swap_DWORD(g_pQspiRegs->SPI_DATA2);
      *pdwReadBuff++ = swap_DWORD(g_pQspiRegs->SPI_DATA1);
      *pdwReadBuff++ = swap_DWORD(g_pQspiRegs->SPI_DATA);
      __asm__("DMB");
    }
    dwBytesToRead %= c_byReadTransferBytePackSize;

    /* Transfer the rest of the bytes (non 16 byte packed) one by one */
    dwQSPIx_SPI_CMD &= ~CSL_APP_CFG_QSPI_SPI_CMD_WLEN_MASK;
    dwQSPIx_SPI_CMD |= (8 - 1) << CSL_APP_CFG_QSPI_SPI_CMD_WLEN_SHIFT;
    while (dwBytesToRead)
    {
      g_pQspiRegs->SPI_CMD = dwQSPIx_SPI_CMD; /* Process Rx command - data in*/

      /* Wait for QSPI to finish the transaction and copy received data from its register(s) */
      s_Qspi_waitIdle();
      *pbyReadBuff++ = (uint8_t)g_pQspiRegs->SPI_DATA;
      __asm__("DMB");

      dwBytesToRead--;
    }
  }
  else if (dwBytesToWrite)
  {
    /* Write data */
    /* Use 16 byte (128 bit) transmissions for faster speed */
    dwQSPIx_SPI_CMD = QSPI_CS0 << CSL_APP_CFG_QSPI_SPI_CMD_CSNUM_SHIFT |
                          ((c_byWriteTransferBytePackSize * 8) - 1) << CSL_APP_CFG_QSPI_SPI_CMD_WLEN_SHIFT |
                          s_getCmdRegCmdPins(true, byNumDataPins) << CSL_APP_CFG_QSPI_SPI_CMD_CMD_SHIFT |
                          (frameLength - 1) << CSL_APP_CFG_QSPI_SPI_CMD_FLEN_SHIFT;
    for (uint32_t i = dwBytesToWrite / c_byWriteTransferBytePackSize; i > 0; i--)
    {
      s_Qspi_waitIdle();

      /* Fill the data buffers */
      g_pQspiRegs->SPI_DATA = swap_DWORD(ToDWORD(pbyDataStream)); pbyDataStream += 4;
      g_pQspiRegs->SPI_DATA1 = swap_DWORD(ToDWORD(pbyDataStream)); pbyDataStream += 4;
      g_pQspiRegs->SPI_DATA2 = swap_DWORD(ToDWORD(pbyDataStream)); pbyDataStream += 4;
      g_pQspiRegs->SPI_DATA3  = swap_DWORD(ToDWORD(pbyDataStream)); pbyDataStream += 4;
      __asm__("DMB"); 

      g_pQspiRegs->SPI_CMD = dwQSPIx_SPI_CMD;
    }
    dwBytesToWrite %= c_byWriteTransferBytePackSize;

    /* Transfer the rest of the bytes (non 16 byte packed) one by one */
    dwQSPIx_SPI_CMD &= ~CSL_APP_CFG_QSPI_SPI_CMD_WLEN_MASK;
    dwQSPIx_SPI_CMD |= (8 - 1) << CSL_APP_CFG_QSPI_SPI_CMD_WLEN_SHIFT;

    while (dwBytesToWrite)
    {
      s_Qspi_waitIdle();

      g_pQspiRegs->SPI_DATA = *pbyDataStream; __asm__("DMB"); /* Fill transmit buffer with data byte */
      g_pQspiRegs->SPI_CMD  = dwQSPIx_SPI_CMD;            /* Start transmission */

      dwBytesToWrite--;
    }
  }

  return TRUE;
}