OPT9221: OPT9221 SYSCLK_IN 48MHz and startup SPI EEPROM requirement 40MHz

minghua

Part Number: OPT9221
Other Parts Discussed in Thread: OPT8241

Hi,

From my previous question about TIC_CLK the answer mentions "a minimum clock period requirement of 15ns". That is 66MHz, so 48MHz is ok.

In another thread about OPT9221 Master Serial Configuretion it says "the max clock frequency used for reading the SPI flash is 40MHz".

Would it mean driving SYSCLK_IN at 48MHz is violating the requirement for startup from SPI EEPROM?

Thanks.

over 8 years ago

0 Praveen Aroul over 8 years ago

TI__Mastermind 49986 points

Hello Minghua,

We have received your inquiry regarding the device OPT9221 and the applications team will get back to you with a response next week.

0 Larry Li over 8 years ago in reply to Praveen Aroul

TI__Expert 3495 points

TIC_CLK is not necessarily SYSCLK_IN (48MHz) or 66MHz (t_cck = 15ns). The 48MHz SYSCLK_IN is internally stepped up by PLL before dividing down for TIC_CLK. You might want to probe the OPT8241 CDK to confirm.

0 minghua over 8 years ago in reply to Larry Li

Intellectual 495 points

Hi, Larry, Thanks for the suggestion. Yes I probed the signal, it is running at 40Mz, that's well in the scope of the spec.

Sensors

Sensors forum

OPT9221: OPT9221 SYSCLK_IN 48MHz and startup SPI EEPROM requirement 40MHz