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Original question:

AWR1243: Alternate Flash Chip?

AWR1243: Alternate Flash Chip?

Rajesh Rangaiah
Prodigy 20 points
Part Number: AWR1243
Other Parts Discussed in Thread: UNIFLASH

Hello, 

I am Rajesh from Macronix. 

One of our customer is working on TI AWR1243 and would like to use our MX25U6435F device with the AWR1243 radar chip, but it's some how failing under test.The MX25U6435E however did pass.

Support contents: Customer is downloading firmware to external Flash with "UNIFLASH" provided by TI.
　　　　　　　　"MX25U6435E" is OK in MXIC Flash, "MX25U6435F" is Not ok.
　　　　　　　　※ The concrete phenomenon seems not to end the Page Program.
　　　　　　　　"MX25U6435E" is stated in the support list of "UNIFLASH", "MX25U6435F" is no description.
　　　　　　　　Customer is waiting for TI 's update of "UNIFLASH" Flash support list.

Can you please check on this request.

Thanks
Rajesh
Mail: rajeshrangaiah@mxic.com.tw
PH: +91 98801 84483

  • 0
    TI__Guru*** 148304 points
    Hi,
    We are checking with our team about updated list

    thank you
    cesar
  • 0 in reply to Cesar
    Intellectual 640 points

    I, and probably many others, would also be interested in seeing an updated flash compatibility list.

  • 0 in reply to ej99
    TI__Guru 58035 points
    Hello Rajesh,
    Could you provide which ES version of the AWr1243 device they are using?
    Also please share the difference between the MX25U6435E and MX25U6435F part.

    In the latest version of the AWR1243 device (ES3.0) we support any serial flash that meets the following requirements:
    1) Meets the QSPI interface timing specs mentioned in the AWr1243 datasheet.
    2) SFLASH supports the SFDP command and responds with JEDEC compliant information regarding the capabilities and command set of the flash. The key fields interpreted by the bootloader are :

    Field Byte Offset
    SFDP Signature [3-0]
    JEDEC Flash Parameter Offset in bytes [0xE-0xC]
    (1-1-4) Read Support [JEDEC Flash Parameter Offset in bytes + 0x2] – bit6
    (1-1-2) Read Support [JEDEC Flash Parameter Offset in bytes + 0x2] – bit0
    (1-1-4) Read Command Code [JEDEC Flash Parameter Offset in bytes + 0xB]
    (1-1-4) Read Dummy Cycles [JEDEC Flash Parameter Offset in bytes + 0xA] – bit[4:0]
    (1-1-2) Read Command Code [JEDEC Flash Parameter Offset in bytes + 0xD]
    (1-1-2) Read Dummy Cycles [JEDEC Flash Parameter Offset in bytes + 0xC] – bit[4:0]

    3) The number of address bytes = 3 (always)
    4) For single data line SPI read – Read Command Code (0xB), Read Dummy cycles (8bit)
    5) The ROM assisted download should work with all flash variants that allow for “Memory mapped mode” and “Page program command (0x2)” with 1 dummy byte and 24bit addressing.
    6) The ROM bootloader performs the read from the FLASH based on the highest capability mode (Quad/Dual/Single) as published by the SFLASH in response to the SFDP command. The commands used also are as published by the SFDP response. So if the Quad read is supported, the expectation is that the Quad Enable (QE) bit is already set in the FLASH. The ROM bootloader would use the Quad mode to perform the read

    Regards,
    Vivek