AWR1243: TestPattern Validation in Xilinx FPGA

Hello ,
The DATA VALID would be high during the period the chirp data is being sent out and will go low until the next chirp data starts. The test pattern is also emulated as 'chirps' , just that the data is fixed rather than actual ADC measurements. So yes, data valid will go low.

Regards,
Vivek

Hi Vivek,

Thank you for  the comment. I believe that my Colleague didn't put up the question properly.

We understand that the DATA_VALID will be low between packets.

Out problem/issue is, there is a large deviation in the difference between the last sample of current packet and the fist sample of next packet. Our observation are:

1) This deviation happens at the start of every packet, all the time.

2) The difference is usually 511, 512 or 513, when the packet size is 512. The difference is around 255 when the packet size is 256.

3) We have estimated that this change happens at start of every new packet by looking at Data_VALID going low.

4)Within a packet, the samples increment by 1, as expected.

5) Across packet also we expect the samples to be incremented by 1 only (not happening). We are not sure, whether this expectation is correct.

Any help on this part would be highly appreciated.

Thanks in Advance,

Santhana Raj

Hello Santhana,
OK, now I understand the issue. The value is expected to the continuous across samples.
If the samples are been generated faster than what the LVDS interface can send out then some of the samples could be missed. Can you increase the value for "TestPattern_Gen_timing" value so that the rate of samples slows down?

Regards,
Vivek

Hi Vivek,

Thank s for the idea.
As you can see in the image earlier, currently the Gen_timing value if 10.667 to generate data at 18.75 MSPS in complex.

We went ahead and tested with Gen_Timing of 10 and 15, but we observed the same issue here also.
The error phenomenon was same

I am not sure why I have to increase the Gen_timing value. The value of 10.667 should result in (200/10.667) = 18.75MSPS.
In bit rate it should be 600Mbps (18.75M*16*2).
The LVDS data line configuration is set to 900Mbps.
So I expect that since the data is generated at 600Mbps and the LVDS is sending out at 900Mbps, there should not be any overflow in the buffers. Can you confirm me whether my expectation is correct??


Thanks for any help on this issue.
Santhana Raj

Hello Santhana,
Your expectation seems correct.
In that case the FPGA seems to be missing some samples for some reason?

Regards,
Vivek

Hi Vivek,

We are not sure about this, because, the data is received properly within a packet. The mismatch is present only at the start of the new packet.

Can you suggest any way to verify/ debug this problem??

Hello Rohith,
Can you increase the Gen timing value of 128 or something higher to reduce the rate at which the samples are generated?

Regards,
Vivek

Hi Vivek,

We have reduced the sample generation time to 8,4,2,1 and finally to 0.5Mbps. (by increasing the Gen timing value as you suggested)

We see that the jump that we were seeing in 18.5Mbps has reduced.

At 1 Mbps and 0.5 Mbps, we see that the first sample of all the 4 lanes in a packet are wrong. They are basically the first 4 values of next packet as seen in the data capture below.

Any help on this issue would be highly appreciated.

One more question,

Reducing data generation speed, reduces the wrong values in captured data. Does this mean that the TI's test generator has issues at very low Gen_timing value???

Thanks a lot, Vivek for your kind explanation about the issue. Now we understand and shall follow as per your suggestions

Currently, we also got ADC data. but in In Initial few chirps the first sample is zero. Can you please point us, what could be the Issue ???

I also have one more question about test pattern

For Slave sensors, do I need to configure the master first to get the test pattern???

Hello Rohith,

For the ADC data are you using the DCA1000 to capture the data?

Regarding the slave sensors, yes you need to configure the master first so that it provides the 40Mhz clock to the slave. Only then can you configure the slave devices.

Regards,

Vivek

Hi Vivek,

For ADC / TestPattern we are NOT using DAC1000.
We have a custom setup to Configure and Capture Sensor data from Xilinx Zynq SoC

In Continuation to earlier post,
>>> Currently, we also got ADC data. but in In Initial few chirps the first sample is zero. Can you please point us, what could be the Issue ???
We have added Chirp Profile Information to ADC data. with this we have not seen any ZEROs at the start of the chirp.
The Issue appers only when you disable chirp profile Info.

Can you please give us a pointer to resolve this issue

Thanks for your support

Hi Vivek,

Only 1st sample of few chiprs (2nd chirp to 6th chirp). all other chirps has non-zero first sample
Please let us know, If you would like know more information

Thanks for your time and support

Hi Vivek,

We have figured out the issue in our DDR storage data path.

Now, we have got the ADC data which seems to be correct.

Thanks your time and support