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Original question:

AWR1243: LVDS Setup and Hold timing requirements

AWR1243: LVDS Setup and Hold timing requirements

Rohith Gourishetty48
Prodigy 190 points
Part Number: AWR1243

Hi Vivek,

As Mentioned In the previous post,

Hello Rohith,
From our transmitter side we the data is expected to be stable 200psec before and after the clk edge.

As per Xilinx experts, This window is very small (Not even half of the period)  to ensure reliable data capture. 

Can you please provide more Information on this..., I mean, How TI ensures relaible data capture with this very small data valid window

  • 0
    TI__Mastermind 24955 points
    Rohith,

    I have assigned this E2E thread to Vivek given the contents of your post. Please allow some time for a response.

    Regards,
    Kyle
  • 0
    TI__Guru 58035 points
    Hello Rohith,
    How can you have half period setup hold time when the clk is DDR? That means after half the period you will actually have the next data coming (after 1100 psec data next set of data comes). Out of 1100psec , 400psec (+-200psec ) is a very large period. I suspect its some issue with the FPGA code. Are you using the Frame clock signal properly? The valid data is available only when the frame clock is available.

    Regards,
    Vivek
  • 0 in reply to Vivek Dham
    Prodigy 190 points

    Hi vivek,

    I mean 1100 spec in the context of period.. very sorry if my context of the question is misinterpreted.

    As per 400psec, i meant it was less than 550psec.

    Any how, my question is in the grounds of pure anxity to know more about the interface.

    As per our latest test reports we are able to sample the data correctly over a span of 500-600psec... (Depending on the nature of the input)

    I would be thankful, if you could share more details about LVDS interface. Again, this request purely in the grounds of anxiety and intrest to get more clarity of the things what I do..

    Thanks a lot, for your continued support

  • 0 in reply to Rohith Gourishetty48
    TI__Guru 58035 points
    Hello Rohith,
    550psec is the theorical max. In the a real transmitter this period will be lesser due to finite rise/fall time and jitter. If you reduce the LVDS rate that will allow a larger window since the time period increases.

    Regards,
    Vivek