This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
I would like to know if it is possible to set the frame duty cycle to 100% by setting the frame periodicity parameter to
(idleTimeConst + rampEndTime) * numOfChirps
If not, what should frame periodicity set to if I do not intend to enable calibrations or monitoring?
Hi
The FFT processing is done outside of the AWR1243 chip, I only intend to collect RAW-ADC data. Having said that, I need to minimize the inter-chirp time as much as possible to fully utilize the AWR1243.
This is my use case.
Given N different waveform configurations ( chirp/profile/frame configurations), Let's say its' N = 2
waveform 1 = 1ms total chirp time, 1ms inter frame time, -> 2 ms frame periodicity
waveform 2 = 2ms total chirp time, 2ms inter frame time, -> 4 ms frame periodicity
In 12ms I can have 2 x waveform1 + 2x waveform2 -> 4ms + 8ms
However, if the inter frame time is 0 ms, I can fired off 4 x waveform1 + 4x waveform2 -> 4ms + 8ms
Thanks,
Dom
Hi,
I understand the inter-frame time must be >=200us. However, when the following parameters were program,
chirpCfg.chirpStartIdx | 0 |
chirpCfg.chirpEndIdx | 3 |
chirpCfg.profileId | 0 |
chirpCfg.startFreqVar | 0 |
chirpCfg.freqSlopeVar | 0 |
chirpCfg.idleTimeVar | 0 |
chirpCfg.adcStartTimeVar | 0 |
chirpCfg.txEnable | 5 |
frameCfg.chirpStartIdx | 0 |
frameCfg.chirpEndIdx | 3 |
frameCfg.numLoops | 128 |
frameCfg.numFrames | 1 |
frameCfg.numAdcSamples | 750 |
frameCfg.framePeriodicity | 3040000 |
frameCfg.triggerSelect | 2 |
frameCfg.frameTriggerDelay | 0 |
profileCfg.profileId | 0 |
profileCfg.pfVcoSelect | 0 |
profileCfg.pfCalLutUpdate | 0 |
profileCfg.startFreqConst | 1435388860 |
profileCfg.idleTimeConst | 300 |
profileCfg.adcStartTimeConst | 440 |
profileCfg.rampEndTime | 2540 |
profileCfg.txOutPowerBackoffCode | 0 |
profileCfg.txPhaseShifter | 0 |
profileCfg.freqSlopeConst | 181 |
profileCfg.txStartTime | 0 |
profileCfg.numAdcSamples | 375 |
profileCfg.digOutSampleRate | 18750 |
profileCfg.hpfCornerFreq1 | 0 |
profileCfg.hpfCornerFreq2 | 0 |
profileCfg.rxGain | 48 |
The AWR will generate the error below once multiple frames of the above setting were trigger
Sub block 0x1011 – AWR_CAL_MON_TIMING_FAIL_REPORT_AE_SB
Error code : 0x5
This is unexpected because all the one time & periodic calibration of various RF/analog aspects are disabled by calling rlRfRunTimeCalibConfig with arlRunTimeCalibConf_t = {0}. Moreover, if the frame periodicity is modify from 3040000 to 3240000. The timing fail report error will go away.
Hi Dom,
In RadarSS, APLL and SYNTH calibrations are done always internally irrespective of bits are enabled or not, the time required for these calibrations must be allocated. And time required for these are 150 and 300usec respectively in addition of 150usec (application of calibration to hardware), which you need to have during inter-frame idle time. RadarSS will send FAIL_REPORT async event if inter-frame time is not sufficient to do these calibrations.This information is explained in ICD (of DFP) Table 9.2 (sl.no 1,2,7).
I have same config at my end and it requires around 1.1ms inter-frame time (15.65msec frame periodicity) to avoid this failure report as on top of above timing constraint RadarSS requires watchdog clearing time as well which increases this time.
For the purpose of capturing the raw data you can ignore this Async event report and proceed further.
Regards,
Jitendra