Compiler/PGA411-Q1: PGA411-Q1-Qusetion

user5901311

Part Number: PGA411-Q1

Tool/software: TI C/C++ Compiler

In datasheet 2017 there are some new fault marker bit which was never appeal in datasheet 2016， such as FLOOP_CLAMP，FGOPEN，And it’s describe is so simple ， I don’t know how to test this fault and what condition will trigger this bit set to 1， Especially FGOPEN can cause Fault pin to high state. So I just want to know more details about this two fault bit， thanks! ( more details see Datasheet2017-page-45)

（1）Oscillator Fault

（2）Exciter Power Supply (Boost) Overcurrent Protection

（3）Exciter Thermal Shutdown

（4）Exciter Power Supply (Boost) Critical Overvoltage Shutdown

（5）Exciter Power Supply (Boost) Undervoltage Fault

（6）Exciter Power Supply (Boost) Critical Undervoltage Shutdown

（7）System Level Communication Test

Above seven was appeared in the safety Report in 2017 (Data:25-oct-16 Version:1.3 )which was a NDA Document ，But I can’t find correspond item in the safety manual2016(SLAA684–February 2016)； Maybe some document we have was older ，Do you have the latest files?

According to the Datesheet-2017 ，if the crc was not right ， the SPI_ERR bit will trigger to 1，but in the process of testing ，I can see this fault only if the register address was mistake，if crc was not correct， SPI_ERR will not trigger ，I don’t understand where I am wrong. ( See Datasheet -2017-page-55)

In the safety manual 2016-page-22， This sentence "The deglitch time for this fault is defined by the IZTHL (bits 7-9) setting in DEV_OVUV6 register."，Personally I think this sentence should changed to “The deglitch time for this fault is defined by the TEXTMON (bits7-5) seting in the DEV_ OVUV4 register ”;( Safety manual 2016-page-22)

Recently we test functional safety ，there is item named as “User EEPROM space crc fault “，We have calculated the right EEPROM CRC and it’s identical value which was storage in the ECCRC bit of the DEV_CLCRC Register ，but I don’t know how to make the FCECRC bit in DEV_STAT1 set 1， and what ‘s relationship the ECCRC with our right CRC value Which we have just calculated before；I’m a little confused about this part，In our testing process we have never see the FCECRC set to 1 happened before， can you give me some instruction?（ More details see Safety manual 2016-page-19）

thanks!

over 6 years ago

0 Clancy Soehren over 6 years ago

TI__Mastermind 23810 points

1. Those faults will detect gross problems internal to the PGA411, but they will be difficult for you to test yourself.

2. The oscillator fault is in the safety manual (section 5.33). Faults 2 - 6 are internal to the boost and are not directly reported via SPI. Item 7 is not in the safety manual because it is not implemented with a specific diagnostic. The "Proposed Detection Method" listed in the Safety Analysis Report explains how to detect such a condition, and in the "Notes" section, it comments that this should be done by an external MCU.

3. It should be able to detect a CRC problem. If the SPI clock is invalid, it should also set the same bits.

4. You are correct. That is a typo in the safety manual.

5. This is an internal test to the PGA411-Q1, so it will be impossible for you to cause it to fail without something abnormal happening inside the PGA411. The MCU can check the value of EECRC against the MCU's calculated CRC to verify that the EEPROM is correct.

0 user5901311 over 6 years ago in reply to Clancy Soehren

Prodigy 45 points

Thanks for your answer ,but we still dotn’t understand about question 3 and question 5;

About Question 3
For example
The original CRC algorithm was list below which has been proved was corrected;

uint16 lPGA411_Crc6(uint32 data_in)
{
uint16 byte_idx, bit_idx, crc=(PGA411_CRC_INITSEED <<2);

for(byte_idx = PGA411_CRC_BYTECOUNT; byte_idx >= 1; byte_idx--)
{
crc ^= ((data_in >> (byte_idx<<3)) & 0x000000FF);

for(bit_idx = 0; bit_idx < 8; bit_idx++)
{
crc = crc << 1 ^ (crc & 0x80 ? (PGA411_CRC_POLYNOM<<2) : 0);
}
}

return(crc >> 2 & PGA411_CRC_INITSEED);
}

But if we just changed the last line and this algorithm turns into like this：

uint16 lPGA411_Crc6(uint32 data_in)
{
uint16 byte_idx, bit_idx, crc=(PGA411_CRC_INITSEED <<2);

for(byte_idx = PGA411_CRC_BYTECOUNT; byte_idx >= 1; byte_idx--)
{
crc ^= ((data_in >> (byte_idx<<3)) & 0x000000FF);

for(bit_idx = 0; bit_idx < 8; bit_idx++)
{
crc = crc << 1 ^ (crc & 0x80 ? (PGA411_CRC_POLYNOM<<2) : 0);
}
}

return(crc >> 1 & PGA411_CRC_INITSEED);
}

And we used this not correct CRC value ,but the SPI_ERR (DEV_STAT4 register)bit will not trigger to 1;

About Question 5

The “EECRC” you have mention in the answer, but I have never find it ?

ECCRC (DEV_CLCRC register) this bit not only can read ,but also can write ;what condition can use it’s write function?

Best regards!

0 Clancy Soehren over 6 years ago in reply to user5901311

TI__Mastermind 23810 points

Question 3:
I will see if I can reproduce this in our lab.

Question 5:
My apologies, it should be ECCRC. In your MCU, you can store the expected value of ECCRC to double check that the EEPROM is correct.

0 user5901311 over 6 years ago in reply to Clancy Soehren

Prodigy 45 points

thank's for you answer ,
about question 5
if we want to pass functional safety ASIL--C ,is this double check EEPROM was necessary??

0 Clancy Soehren over 6 years ago in reply to user5901311

TI__Mastermind 23810 points

For question 5, I cannot comment about if that step is necessary for ASIL-C. ASIL levels depend on the system design.

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Compiler/PGA411-Q1: PGA411-Q1-Qusetion