Other Parts Discussed in Thread: AWR1243
Since the highest clock rate of AWR1642 is 450MHz, which means 900Mbps for DDR data transfer, why in section "5.10.4.1 LVDS Interface Timings" of the datasheet, there is a LVDS_CLK at the frequency of 900MHz? Following the above logic, the data rate would be 1.8GHz for a 900MHz clock. Which point do I get wrong?
