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AWR1243: LVDS protocol

Fabian Schwartau
Intellectual 270 points
Part Number: AWR1243

Hi everyone,

is there any detailes description on the LVDS-Protocol of the AWR1243 available?

It is not clear how the samples are transfered over the lanes when used in parallel. The programmer guide gives an introdution (section 2.1.2.1) about the transferred data and the order but there is nothing about the parallel lanes, how they are involved in which order.

Also I cannot find any information on how the synchronize the LVDS receiver on byte and words. Are there some test patterns send at the beginning of each transfer? Where are they defined?

Thanks,

Fabian

  • 0
    TI__Expert 3610 points

    Hello Fabian,

        We are in process of putting up a document for the LVDS protocol. Below timing diagram explains the protocol for 16 bit per sample LVDS data as below

    regards

    AK

  • 0 in reply to Abdulraheem Killedar
    Intellectual 270 points
    Hi,
    thanks for the info. But my request is quite urgent. I have to figure this out within the next few days. Is it possible to transmit a sync word at the start of each transmission? If it is not possible, can I use the sanity test for synchronization?
    The problem is, that as far as I understand the frame clock will not be enough as the state of a de-serializer in an FPGA (Xilinx) is not defined at startup. So it is not possible to get a bit-synchronized parallel stream from the de-serializer which will make the frame clock useless. That is why it is common to send a sync word at the beginning - but I cannot find any definition of that sync word.
    By the way: Is the source code for the TSW1400 accessible? So I could have a look how you implemented that.

    Regards,
    Fabian
  • 0 in reply to Fabian Schwartau
    TI__Expert 3610 points

    Hello Fabian,

         Its not needed to tramsmit the sync pattern and its not possible  to send it at the beginning also. LVDS Frame clock with bit clock will be enough for the data deserialization.

    In TSW1400, the FPGA Hard macro-Deserializer deserializes the data and the Frame clock too. this would keep the data and Frame clock delays same. Frame clock transition from Low to high , marks the valid data capture start.

    Let me know if you need more information.

    regards

    AK

     

  • 0 in reply to Abdulraheem Killedar
    Intellectual 270 points
    Hi Raheem,
    maybe this works on the FPGA you used in the TSW1400 board, but it does not work for Xilinx FPGAs. Please correct me if I am wrong about that - I am not the FPGA guy at our project. As I understood the Xilinx de-serializer has an undefined state at startup. Which means that the first bit (once the frame valid is true) my be at a random place in the deserialized data. This is the case for each de-serializer individually. So, if the valid line got high on the 3rd bit of its de-serializer, it might be the 6th bit for the data0 lane and the 1st bit for the data1 lane. How should I know that?
    Let me get back to the samity test mode of the chip: As far as I understood I can use it to transmit known pattern on the LVDS bus. So it would fit my requirement to send a know pattern and synchronize on that. My quation is: How can I turn that test mode on? I cannot find any API calls in the mmwavelink to do that.
  • 0 in reply to Fabian Schwartau
    TI__Expert 3610 points
    He llo,
    Please refer to the following in the AWR1xx Interface control document (part of the DFP release)

    AWR_DEV_TESTPATTERN_GEN_SET_SB

    regards
    AK