PGA450-Q1: PGA450-Q1EVM-S

Hi Ganjikunta,

The PGA450-Q1 internal 8051 micro must be in the RESET state to use SPI communication. See data sheet section 7.4.3 RESET for details:

7.4.3 RESET
The PGA450-Q1 can also be put into a RESET state where the microcontroller is not active. During this state,
SPI is the only digital interface that can be used. The low-side drivers can still be triggered to begin an ultrasonic
burst and the analog front-end and digital data path can still store the returned echo signal in the FIFO RAM.
However, any processing of the FIFO RAM by the internal microprocessor to determine the location of an object
does not occur. The FIFO RAM data can be read over SPI, allowing an external microprocessor to process the
data.
While the microcontroller is active, the MICRO RESET test register is the only register accessible through SPI.
The device must be put into the RESET state before sending additional SPI commands.
The maximum current (VREG not charging) in the RESET state is 15 mA.
To put the microcontroller in reset, write a 1 to bit 0 of the MICRO RESET (address 0x2F) test register. Transmit
the TEST Write SPI command in the following order: 0x16, 0x2F, 0x01.
To bring the microcontroller out of reset, write a 0 to bit 0 of the MICRO RESET (address 0x2F) test register.
Transmit the TEST Write SPI command in the following order: 0x16, 0x2F, 0x00.

Once in the RESET state, you will be able read and write to any of the registers just as you would through UART or LIN.

You can port the UART code from the TIDA-00151 UART & LIN Demo Firmware for PGA450-Q1 into a SPI equivalent.

For example, when executing a burst/listen time-of-flight command (command1 from the example code), you will need to perform a SPI ESFR write of the following:

PWR_MODE = 0x03; // VREG_EN (D1)=1, ACTIVE_EN (D0)=1, ready for ultrasonic burst
EN_CTRL = 0x00; // Clear FIFO memory before burst

...

PWR_MODE = 0x01; // VREG disabled for better noise, ACTIVE mode remains enabled
EN_CTRL = 0x0C; // Enable Echo Capture

... (wait for record cycle to finished --> couple of milliseconds)

// Read back FIFO registers.

The primary limitation of the SPI mode of operation is that you cannot utilize the custom programmability of the 8051 MCU.