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Original question:

TDC7200: TDC7200 delivers implausible TIME1 / SPI transfer is not reasonable

TDC7200: Unplausible TIME1 readings, multiple result clusters

Matthias Welwarsky1
Prodigy 70 points
Part Number: TDC7200

Hi all,

I'm having a problem with the following setup:

- 10MHz system clock

- 500kHz square wave 50% duty cycle on input START

- 500kHz square wave 50% duty cycle on input STOP.

- Phase between START and STOP is 180° to achieve a 1µs interval.

- 40 calibration cycles, before each measurement

- 1 stop, no cycle averaging

With these conditions, I get two distinct result clusters, one at 1µs, a second one at 3µs, almost exactly 2µs apart. This happens to be the clock period of a 500kHz clock. See the attached file for a set of 300 measurements.

tdc7200_2.xls

  • 0
    Prodigy 70 points

    From other sources () I learned that there is a guard time to observe, after arming the TDC7200 for the next measurement, before the START signal may arrive. It's not explicitly stated in the data sheet except in the recommended working conditions as T_TRIGGSTART (5ns nominal). Can you confirm that such guard time is required and if it might explain the effect I'm seeing?

  • 0 in reply to Matthias Welwarsky1
    TI__Mastermind 27950 points

    Hi Matthias,

    Considering the TDC7200 was created primarily for time-of-flight use-cases (non-continuous input signals), rather than continuous clocking at the START and STOP pins, it is possible that there is a required guard/delay time to observe. It is likely this continuous clocking use-case was not validated due to it being a special use-case, and why it is not accounted for in the working conditions section.

    I have read the discussion of your linked external source, and I agree with the conclusion of the guard time requirement. If the guard time is problematic, I recommend using a microcontroller with a timer based capture/compare input instead of the TDC7200.