Other Parts Discussed in Thread: AWR1843
Hi,
We are interested in loading raw ADC data back into the AWR device for testing purposes. We are aware that we have to use the Data Modification Module (DMM) for this purpose through the HIL lines. We have referred to the TRM doc of AWR1843 to understand the working of DMM and the register functions.
My question is:
1) We are unable to get the timing diagram to communicate on the HI/DMM lines.
2) Is there any reference code or steps that the external processor has to do to communicate over the DMM lines. We understand that this has to send data as per the chirp timing. But it is not clear to us on how to send one chirp ADC data itself.
3) Have these DMM lines used in any other processors like TDA or similar. Can we take some reference code from there?
4) We understand that the current version of DCA1000 doesn't have support for loading the data back through DMM lines. But my question here is "Does TI have any plans to update this hardware or release any new hardware to perform this? if Yes, what is the approx timeline here?
5) Will DCA1000 FPGA source files be shared with us?
Thanks in advance
Santhana Raj
