Hi Vivek,
I captured the LVDS_TXP/M and LVDS_CLKP/M signals (image below at clk = 300MHz & ddr):
- the lvds_clkp/m differential voltage is about 268mV and
- lvds_txp/m0 (lane 0) differential voltage is about 632mV.
The specs is 250mV-450mV, do these output levels seem right or the output configuration settings for clk and txp/m0 are off.
Kind regards,
Long