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Original question:

MMWCAS-RF-EVM: MMWCAS-RF-EVM

MMWCAS-RF-EVM: MMWCAS-RF-EVM

Michael Su
Intellectual 610 points
Part Number: MMWCAS-RF-EVM
Other Parts Discussed in Thread: AWR2243,

Hi,

Now, we  are designing our AWR2243 RF board by referring to the TI EVM, MMWCAS-RF-EVM, and  following the TI PCB stackup  for the first version, but we find one question,

The trace width of layer 1 (77GHz RF lines of TX and RX ) is 8.4mils on the TI PCB file, but it is 10.5mils in the impedance table of TI stackup document , which one is correct ?

The trace width of layer 3 ( 20GHz Lo signal) is 5mils on the TI PCB file, but it is 5.1mils in the impedance table of TI stackup document, which one is correct ?

Thanks

Michael Su

  • 0
    TI__Mastermind 31680 points

    Hello Michael,

    Our expert will review your query and get back to you by early next week.

    Thankyou for your patience.

    Regards,

    Ishita

  • 0
    TI__Guru 58035 points

    Hello Michael,

    Please use the width in the PCB file.

    regards,

    Vivek

  • 0 in reply to Vivek Dham
    Intellectual 610 points

    Hi Vivek,

    Thanks for your reply

    Michael Su

  • 0 in reply to Michael Su
    TI__Mastermind 18500 points

    Hi Michael, 

    Just to add some more detail here that might be helpful to you and future user of the MMWCAS-RF-EVM files. 

    The impedance table only describes non-RF/non-LO high-speed digital controlled impedance lines used in the design. For example, the L1, 10.5 mil width lines are used for 40MHz clocking lines on the top layer. The L1, 6.5 mil 100ohm differential lines are the CSI2 fan-out. 

    The RF lines are not described in this table. The reason for that is that many PCB fabricators, including the ones we worked with, sometimes interpret a "controlled impedance" fabrication directive to mean that the specified width lines in CAD should be adjusted in CAM prior to fabrication. The adjustment of line widths will be done based on the fabrication house's own analysis of the stack-up and transmission lines, and their lamination process experience. In my case the easiest way to make sure the final RF fabrication most closely matched the CAD intended dimensions, was to simply remove the RF/LO lines from their controlled impedance directives.

    In this case, I aligned with the fabricator on selecting line widths for the high-speed digital lines as part of the stack-up selection and used those line widths in the CAD. So at least with my selected fabricator, there would be no difference in CAD, final CAM and intended fabrication dimensions. 

    You should discuss this point with your selected fabrication house and make sure each RF and high-speed digital controlled impedance line is being fabricated as expected. It is best to not assume that these lines will be fabricated just as included in your CAD unless you have aligned.

    Thank you,

    -Randy

  • 0 in reply to Randy Rosales
    Intellectual 610 points

    Hi Randy,

    So, in your  experience, you will discuss the PCB stackup and controlled impedance with the PCB fabricator before doing the CAD for high-sped digital signal, right ? how about the impedance control of RF/LO line ?  you calculate them by yourself based on the decided PCB stackup ?  also, why both digital signals and RF line are 50 ohm impedance control, but the line width is 10.5mil  and 8.4mil individual on the top layer of MMWCAS-RF-EVM ?

    By the way, in my experience, I will use the two reference ground plane for the strip line to calculate the impedance and get the better performance, but in the CAD file of MMWCAS-RF-EVM, some CSI2 differential signals are routed on the layer 6 with the reference ground plane, layer 7 and digital signals layer, layer 5,  its performance is OK ?

    Thanks

    Michael Su

  • 0 in reply to Michael Su
    TI__Guru 58035 points

    Hello Michael,

    The digital lines are stripline or micro strip designs while the RF traces are CPW design. Also at 80Ghz there would be some differences in impedance.

    Regards,
    Vivek

  • 0 in reply to Vivek Dham
    Intellectual 610 points

    Hi Vivek,

    How should I calculate the impedance of the CPW ?

    The feed lines of antenna are CPW design, but the 20GHz LO signals should still be the strip./ micro strip line design, right?

    Thanks

    Michael Su 

  • 0 in reply to Michael Su
    Intellectual 610 points

    Hi,

    any update ?

    1.  I calculate the impedance of the antenna feed line (GCPW) based on the stackup and trace width in the TI's PCB file and use the impedance equation for the GCPW trace, the result

        cannot meet our expectation, 50 ohm, why ?

    2. The aforementioned question, in the CAD file of MMWCAS-RF-EVM, some CSI2 differential signals are routed on the layer 6 with the reference ground plane, layer 7 and digital signals layer, layer 5, 

         the layer 5 signal trace will not affect the signal integrity of CSI2 signal ?

    Thanks

    Michael Su

  • 0 in reply to Michael Su
    TI__Guru 58035 points

    Hello Michael,

    1) We rely on HFSS simulations for impedance estimation. We don't rely on calculators for 80Ghz since every small aspect like solder mask etc. impacts the impedance. We have confirmed our PCB trace impedance by measurements as well.

    2) Between L5 and L6 there is a 10mil core which makes the L5 layer much further away from L6 as compared to L7. So the L7 gnd will be dominant factor for the impedance. If you want a better control you could have Gnd on L5 also  above the CSI lines and compute the impedance as asymmetric stripline.

    Regards,
    Vivek

  • 0 in reply to Vivek Dham
    Intellectual 610 points

    Hi Vivek,

    Understood!

    Thanks

    Michael Su