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AWR1843BOOST: some question about function of MmwDemo_dataPathConfigBuffer

Gmsy Bryant
Expert 1650 points
Part Number: AWR1843BOOST
Other Parts Discussed in Thread: AWR1642, AWR1843,

Hello,

When i read the function of MmwDemo_dataPathConfigBuffer,i have a question.

If we use demo11 about MRR && USRR,and we use two subFrame.When we alloc L2 memory about part2,for example twiddle16×16_1D.

According to the code, obj will be increased during MRR && USRR memory allocation, but obj will point to the same memory space address, that is, USRR  twiddle16×16_1D will overwrite the memory space of MRR twiddle16×16_1D.

Or did I misunderstand the code? Please ask TI engineers to confirm the following.

Thanks a lot!

Bryant

  • 0
    TI__Guru*** 143714 points

    Hi,

    Your understanding is not correct.

    The same table twiddle16×16_1D is used for both subframes MRR and USRR. So the same allocated memory section is used for both subframes. The memory is not overwritten

    thank you

    Cesar

  • 0 in reply to Cesar
    Expert 1650 points

    Hello,Cesar

    If MRR 1D-FFT is 256 point,however USRR 1D-FFT is 512 point,the same table twiddle16×16_1D is use in common？Can the result still be correct？

    Thanks a lot!

    Bryant

  • 0
    TI__Guru*** 143714 points
    Hi,
     
    You are correct, I was wrong.
     
    There are separate windowing and twiddle tables for USRR and MRR sub-frames. They are allocated in buffers which are not overlaid.
    So, the buffers are not overwritten
     
    Sorry for the confusion
     
    Please see the comment in the dss_data_path.c
     
    “*   Memory locations that correspond to the windowing functions, and  twiddle factors, and
    *   estimated mean chirp need to be saved between sub-frames and as such cannot be overlaid.
    ”
     
            /* L2 allocation (part 1)
               The L2 hallocation is done in two parts, the first part consists of memory buffers that can be
               shared between the two subframes. The 2nd part consists of memory buffers that hold state
               information and constants (like the twiddle factors, or the windowing array). These
               cannot be shared (or overlaid in any way).
     
    /**
    *  @b Description
    *  @n
    *   This function assigns memory locations to the different data buffers used in the MRR design.
    *
    *   Processing radar signals require a large number of scratch buffers for each step each
    *   of the processing stages (be it 1D-FFT, 2D-FFT, 3D-FFT, detection, angle estimation etc.
    *   However, since these stages occur serially, the memory assigned to a scratch buffer
    *   used in a previous stage can be re-used in the current stage. The Macro MMW_ALLOC_BUF
    *   in the following code allows specifying the start addresses such that the memory
    *   locations can be overlaid for efficient memory utilization.
    *
    *   In the MRR TI Design, there are two sub-frames per frame, and both sub-frames are processed
    *   separately. Therefore, nearly every scratch buffer memory location can be overlaid
    *   between the two. The allocation code is called twice to allocate memory for both
    *   sub-frames.
    *
    *   Certain memory locations are only necessary for a given processing path and are left
    *   unassigned for different programming paths.
    *
    *   Memory locations that correspond to the windowing functions, and  twiddle factors, and
    *   estimated mean chirp need to be saved between sub-frames and as such cannot be overlaid.
    * 
    *  @param[in,out] obj             data path object.
    *
    *  @retval na.
    */
  • 0 in reply to Cesar
    Expert 1650 points

    Hello,Cesar

    Thank youi very much!

    I have another question.Does AWR1843 have HSRAM.I remember AWR1642 have a HandShake Ram which size is 32K.

    If memory is not enough,can i use HWA M0~M3 to be memory?What are M0~M3 respective sizes？16K each？

    Thanks a lot!

    Bryant

  • 0
    TI__Guru*** 143714 points
    Yes, it does have HSRAM and you can use also the HWA memories. 16K each
     
    Thank you
    Cesar
  • 0 in reply to Cesar
    Expert 1650 points

    Hello,Cesar

    Can HWA memory be read and written directly by address?It's on the same address bus as L1/L2/L3, right?Are reads and writes slower than L1/L2/L3?

    Thanks a lot!

    Bryant

  • 0
    TI__Guru*** 143714 points
    Yes it can, the latency is similar to L3. Which is higher than L1/L2
     
    Thank you
    Cesar
  • 0 in reply to Cesar
    Expert 1650 points

    Hello,Cesar

    Today i use ccs and awr1843boost and i want to use address to read and write the HWA memory,and i find that hwa memory can not be write,and when i read the memory,it is dirty.

    Do I need to enable the HWA hardware function before I can read and write the HWA memory address?Are HWA memory addresses set to read and write permissions?

    Thanks a lot!

    Bryant

  • 0 in reply to Gmsy Bryant
    TI__Guru*** 143714 points

    Did you try to write/read the HWA memory with CCS or with C code?

    You should try with C code

    thank you

    Cesar