AWR1642: Resets causes, and bootloader's SPARE9 values

Hi,

SPARE9 register is being updated only when bootloader comes in the execution flow.

2) SOC_softReset causes R4F core reset, control flow doesn't go to bootloader but re-init current application execution. so you won't see SPARE9 updated in this case.

3) that function is to enable Watchdog reset functionality doesn't do the WDT reset. Follow these e2e threads to cause a WDT reset.

https://e2e.ti.com/support/sensors/f/1023/t/816030?RTOS-AWR1642-How-to-reset-AWR1642-with-SOFTSYSRST-

https://e2e.ti.com/support/sensors/f/1023/t/886100?IWR1443-IWR1443-reboot

https://e2e.ti.com/support/sensors/f/1023/t/835998?CCS-AWR1642-how-to-using-Watchdog-reset-in-AWR1642

So when device actually gets reset due to Watchdog timer expires then control flow goes to Bootloader and there it checks and updates SPARE9 with WDT as cause of reset.

4) Bootloader reads TopRCM and RCM registers to gets the cause of reset and combinigly set both of it into SPARE9 register. and clears both of these topRCM/RCM registers, so at the application you may not see these two registers being set with the values.

https://e2e.ti.com/support/sensors/f/1023/p/850397/3145675#3145675 (here decoding of RCM to SPARE9 is explained).

5) As any of SPARE registers are being used by the firmware (BOotloader) or application so those are not explained in TRM. But ToprCM and RCM cause of reset registers are explained in TRM.

MSS has internal watchdog which needs to be configured and follow answer (3) above for steps to cause a WDT or Warm reset.

Regards,

Jitendra

Hi Jitendra,

Jitendra Gupta said:

that function is to enable Watchdog reset functionality doesn't do the WDT reset.

Note that I wrote ".. With watchdog enabled, "   .   The SoC reset (triggered by writing invalid key) is due to watchdog reset after using that SoC api call.  

Jitendra Gupta said:

4) Bootloader reads TopRCM and RCM registers to gets the cause of reset and combinigly set both of it into SPARE9 register. and clears both of these topRCM/RCM registers, so at the application you may not see these two registers being set with the values.

All my values are from SPARE9, thus I don't understand this point you making. Could you clarify.

Jitendra Gupta said:

MSS has internal watchdog which needs to be configured and follow answer (3) above for steps to cause a WDT or Warm reset.

See above again - the watchdog is configured;  it is the same watchdog - RTI based - as per the mmwave SDK driver as I glanced.  This causes the resets I observe from SPARE9 as my original question ...

So no, i don't think this is answered. 

Hi Jitendra,

Jitendra Gupta

that function is to enable Watchdog reset functionality doesn't do the WDT reset.

Note that I wrote ".. With watchdog enabled, "   .   The SoC reset (triggered by writing invalid key) is due to watchdog reset after using that SoC api call.  

Jitendra Gupta

4) Bootloader reads TopRCM and RCM registers to gets the cause of reset and combinigly set both of it into SPARE9 register. and clears both of these topRCM/RCM registers, so at the application you may not see these two registers being set with the values.

All my values are from SPARE9, thus I don't understand this point you making. Could you clarify.

Jitendra Gupta

MSS has internal watchdog which needs to be configured and follow answer (3) above for steps to cause a WDT or Warm reset.

See above again - the watchdog is configured;  it is the same watchdog - RTI based - as per the mmwave SDK driver as I glanced.  This causes the resets I observe from SPARE9 as my original question ...

So no, i don't think this is answered. 

 .. Just in case that part 3) was not scanned by you in all details, this is what I wrote:

3.  With watchdog enabled,  after executing  SOC_triggerWarmReset, which should issue warm reset , I get :

0x028a028a   , and  have few questions here :

   - With system originally out of NREST (by button),  I expected 0x00990028a , i.e. the memory effect.  Why is it not here?

    -  The 0xa = MSS topRCM  reset due to MSS WDOG ok, but

        0x028 = 0010_1000   == ??  for mssRCM  what is this value?  I don't see this bit pattern on the link referred to above on SPARE9, or  from the Tech Ref manual for x1642.

Again, No memory effect I see,  and some un-expected pattern .

Hi,

It is OR of different reset cause. 

0x28A : 

SPARE9 [11:4] = current MSS reset cause (mssRCM-> RSTCAUSE)

SPARE9 [3:0] = current system reset cause (topRCM->SYSRSTCAUSE)

0x28-->  OR of below two values

0000_1000 : Warm Reset 

0010_0000 : CR4 reset because of Software trigger.

0xA --> “1010” : Warm reset because of MSS Wdog. 

Looks like WDT reset happens multiple times so both of 16bit values are same (WDT RESET cause).

Regards,

Jitendra

Hi Jitendra,

Jitendra Gupta said:

SPARE9 [11:4] = current MSS reset cause (mssRCM-> RSTCAUSE)

SPARE9 [3:0] = current system reset cause (topRCM->SYSRSTCAUSE)

Per the above definition of the bitfields, 

bit 0 to 3  (4 bits) is topRCM->SYSRSTCAUSE,   thus it should contain  0xA only.

bits 4 to 11  (8 bits)  is mssRCM->RSTCAUSE ,  and thus should contain 0x28 per the given above map;   

Hex 0x28   / dec 40 is  bit pattern  0010_1000 , which I quite agree with your map above, but where in the TRM is mentions that it can be OR'ed with the Warm reset  bit pattern ... ?

I didn't find mentioning of possible OR'ing of those bit maps, or just possible OR'ing of one specific  that Warm reset can be ored with others. 

Perhaps there is another doc?

Thank you for the explanation however.

Jitendra Gupta said:

Looks like WDT reset happens multiple times so both of 16bit values are same (WDT RESET cause).

No, this I observe from NRESET, immediately followed by single MSS WDOG reset.  SPARE9's memory then is same  (as I wrote above).

Can bootloader actually maintain SPARE9 memory if it's the MSS WDOG reset?

Because it looks like as for case of NRESET it cannot / doesn't have this memory.

ORing part is not of any document but got this info internally.

SPARE register value is retained over warm reset but not over nRESET.

Regards,

Jitendra

Jitendra Gupta said:

SPARE register value is retained over warm reset but not over nRESET.

Could I double check on this reply :   do you perhaps mean  to also include MSS Wdog case of NOT preserving SPARE9?  

i.e, was I observe when you get bit pattern 1010  / hex 0xA   as I given in above posts.

I 've repeated it multiple times now, and every time the history part of SPARE9  only contains equal  0xA after just 1 MSS Wdog reset.

Hi,

Please provide me few days to check your confusion here and provide the detailed info.

Regards,

Jitendra