TMP102: Two-Wire I/F output delay

user6004480

Intellectual 630 points

Part Number: TMP102

Hi expert,

We are desk-checking TMP102 Two-Wire I/F timing requirements.

How may TMP102 SDA output delay(MAX,MIN) at Read access, should we consider ?

over 4 years ago

0 Josh Wyatt over 4 years ago

TI__Guru* 91206 points

Dear Yuki -

Thanks for posting. Could you help us understand specifically which I2C timing spec you are asking about?

0 user6004480 over 4 years ago in reply to Josh Wyatt

Intellectual 630 points

Dear Josh

Thank you for reply.

We want to know two timing spec described in attached file.

timing1. SCL fall to SDA valid time (max)
timing2. SDA hold time (min)

We want to confirm that Controller can canpture Read data from TMP102.

Two-Wire IF output delay.pdf

+1 Josh Wyatt over 4 years ago in reply to user6004480

TI__Guru* 91206 points

Dear Yuki -

1. This device does not support clock stretching, nor is it in charge of the SCL line - this parameter applies more to the MCU, the pullup resistors and the bus capacitance of the circuit.

2. SDA hold time for I2C devices is minimum 0 + 300nSec.

We have no reports of anyone having basic issues with I2C. If you have or suspect issue, please post full schematic, with MCU and pullup resistors shown and any o'scope or logic analyzer captures.

0 user6004480 over 4 years ago in reply to Josh Wyatt

Intellectual 630 points

Dear Josh,

Thank you for replay!

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TMP102: Two-Wire I/F output delay