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Original question:

PGA305: how to configure the sampling rate

PGA305EVM-034: ADC sampling rate

FRANK1
Expert 8545 points

Part Number: PGA305EVM-034

Hi sir,

A customer is using TI PGA305 EVM board, he have a query on ADC sampling rate.

In regards to the 1024 us sampling rate,

if I wanted to sample at 10 -15 Hz , is the ADC sampling rate still fixed at 1024 us?

or does this decrease with frequency? Our use case may work with the sampling rate of 1024 us,

but we are not sure if the same sampling rate is constant when we work in the 10 - 15 Hz ranges.

Thanks for your clarification.

Regards,

  • +1
    TI__Mastermind 31655 points

    Hello Frank,

    The PGA305 converts continuously, with an output (DAC update) period of 512us. The 1024us sampling rate is only in reference to the filter coefficient table. In any case, the sampling rate of the delta-sigma ADC is fixed at 1Mhz, and has a decimation ratio that results in an internal output period of 128us. The PADC/TADC registers are updated at this rate. The output of the DAC is slower, which is where the 512us output rate comes in. 

    The main point, however, is that the ADC is constantly sampling. You are free to read the PADC data at 10-15Hz, but you cannot slow down the sampling.


    Regards,