TMUX1108: Interference when D pin of multiple MUX shorted and cascaded to TIA

Hey Deepak,

Sorr for the delay here. 

Deepak Sharma said:

Can I operate the TMUX1108 IC with +/-2.5 supply for rail-to-rail operation ie for input analog of +/-2.5V range or some headroom is required?

Yes TMUX1108 can operate from +/-2.5V rail-to-rail with no headroom required. 

Deepak Sharma said:

For minimum leakage, and minimum capacitance/parasitic, we are using four TMUX1108 IC to probe 32x32 sensor array (image attached). By mean of enable pin and GPIO we want to characterize (in a time multiplexed manner) a specific sensor among 1024 possible positions in 32x32 crossbar architecture. As attached, will there be any offset/interference/perturbance in multiplexer output if we short D pins of four TMUX1108 (1:16 MUX is shown for representation purpose) and further gives to the input of transimpedance amplifier for measurement of 0.1nA to 100 nA?

Shorting the output of 4 muxes will short the other off drain capacitance together as well. Assuming 1 channel turned on and the other 31 are off, you'll see (31*60pF + 65pF) 1925pF or 1.925nF capacitance on the output. This will greatly reduce the bandwidth of the device as well. The leakage will also increase by the same proportion. So your 0.01nA would be 0.31nA typical. You could try to reduce the leakage and capacitance that is accumulated by using 8 of the TMUX1111's instead. It'll be more devices but this big increase in off-capacitance is something that is hard to work around when looking to short devices together to make something like a 32:1 mux. 
Another recommendation to keep leakage low would be to guard your rails ( see : Guarding in Multiplexer Applications)

Deepak Sharma said:

At constant temperature and +/-2.5V can we assume that Ron = 125 ohm and 1.5 pF OFF capacitance?

I'm not sure where you're getting these values from. TMUX1108 has atypical RON of 2.5ohms and capacitance of 65pF. 

Deepak Sharma said:

Could you please clarify in detail where exactly these capacitances [CS (Off), CD (Off), CD, CS (On), CIN] are building up when we connect D pin to any of the selectors say S1? For your reference I am attaching one more image, kindly evaluate that.

So three of these images are correct but the last one is not. CIN is the capacitance on the control input. 

Another key distinction here would be the image with CS(ON) and CD(ON). The datasheet can be a little confusing here but the on-capacitance listed is the total CON. So while we typically model this with CS(ON) and CD(ON) on each side of the switch, the 65pF isn't multiplied by two. You can think of it being shared across the two caps. So 32.5pF each for a total of 65pF.

Let me know if this was all clear and if there's anything else you may need!

Thanks,
Rami

Hey Deepak,

Deepak Sharma said:

How is the RC delay of the switch calculated? Is it R_ON (source-drain resistor in ON state) multiplied by total C_ON (effective capacitance from multiple ICs) ? or it is R_ON + R_L multiplied by total C_ON (effective capacitance from multiple ICs) ie will load at drain terminal plays any role in the switching dynamics? (test circuit attached)

The load definitely plays a role and often times will be more of a determining factor in timing than the actual switch. Since timing specs are often taken at the 10/90 of the output relative to when the input hits 90/10, you for sure need to account for the RCload. You can look in the Overview of the test setups in the datasheet to get a better understanding (section 8.1).
Additionally, we have a good FAQ on how to calculate this as well, in case it helps make things clearer : [FAQ] How do I Approximate Propagation Delay and Channel to Channel Skew in an Analog Switch/Multiplexer?

Deepak Sharma said:

Say TMUX is operating with bipolar supply +/-2.5V, are we supposed to drive the guard rings with precision opamp where non-inverting input of opamp is forced to VSS of TMUX ie -2.5 V ? or non-inverting input of precision opamp has to be grounded?

The idea here is to get the trace and guarding to be the same potential so grounded the opamp input should get you there, otherwise you'd be adding a bias. 

Deepak Sharma said:

if a square pulse of 10 mV, 30 nsec passes (S to D or D to S) through TMUX1108 alone (one IC) of switches, how much maximum distortion in input pulse can happen due to switch parasitics?

Is 30nsec the pule width? I believe question 1 covers this. It would be load dependent here but if we pretend that it's going into a high impedance node with no capacitive loading (ie only the device RC having an effect), we can estimate this by using the max RON and CON (~5ohm and 65pF). I come up with 3.25ns. How you're defining the distortion will matter on where you want to measure from. Fro example, If you're looking for the 90% output then 2*tao(your RC constant) would be about there. If you're wanting the 50 to 50 swing then 1RC would be enough. 
To truly estimate the distortion the load would be necessary though and in a lot of cases the mux won't be nearly as impactful. 

Deepak Sharma said:

Frequency domain analysis: Distortions in nsec pulses (square to triangle) will be because of the lowest frequency poles? Is there a way to compensate for the effect of these poles by introducing zeros in the transfer function? Implementation of the same is bothering me…!

What are you defining as distortion here? If you're concerned with the bandwidth or the propagation delay I'm not sure if there is a good way to introduce zeros in the transfer function to reduce this. What type of signals do you plan to actually pass through the mux (ie frequency, voltage)? Based on the above it seems you're looking for 10mV @ 33MHz. I'm a bit skeptical that using 4xTMUX1108 would work here. The BW of just one device is 90MHz. Adding the off-capacitance of the off channels of 3 others would be pushing the limits since when the off capacitance is a bit higher and when you tie the outputs together the bandwidth would greatly reduce. You may want to test this out yourself on your board before finazlizng any layouts.  

Deepak Sharma said:

TINA-TI spice model for TMUX1108 is not available however IBIS model is provided by TI which is going very difficult to simulate, even I could not find a single source that helps me to import IBIS model in “updated LTSPICE, TINA”…!

A new IBIS model is in queue and will be released by the end of the year. The PSPICE for TI model is also in queue for development but in the meantime, you can create the model using passive components. See [FAQ] What if my Analog Switch/Multiplexer is Missing a PSpice Model?

Deepak Sharma said:

will this calculation be valid even if "we disable 3 ICs, enable 1 channel of 1st IC is ON" ie contribution of parasitics when ICs are disabled with GPIOs?

I actually have had a huge oversight on this. Sorry for the confusion here but you wouldn't add all 8 signal paths from each device. The outputs would only see the drains, so you would just need to add 1 CD(OFF) from each device present. So in the case of the 4xTMUX1108 you would only add 3 CDOFF's and then 1x(CON). So your capacitance would actually be 65 (CON) + 3x60 (CDOFF) = 245pF.
If you went with the TMUX1111 you would need 8 devices so 17(CON) + 7*10 (CDOFF) = 87pF. I would still think here that the TMUX1111 would be pushing it on meeting your needs but would offer the best chance of success. 

Another thing to note is that this image does not look quite correct for CDS(OFF)

What you've modeled is the feedthrough capacitance (sometimes labeled Cpd or CF). It should be two different parasitic caps to ground, as you previously drew. Here's another image that may help make things clear.


Thanks,
Rami