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TS3DV642 - Pull up resistors

Hirotaka Matsumoto
Guru 27585 points
Other Parts Discussed in Thread: TS3DV642, TCA9545A

Hi all,

Would you mind if we ask TS3DV642?

Please refer to the following file;
0724.20141003_DVI_TS3V642.pdf

Our cusotmer would like to use TS3DV642 and switch I2c signals.

Pattern1:  1Master - 1Slave but, Master and Slave is changed at some situations(unfixed)
Pattern2:  1Master - 2Slave (fixed)
Pattern3:  2Master - 1Slave (fixed)
(We wrote detailed information on the attachment file.)

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Mastermind 45575 points

    Hirotaka,

    If you are translating voltage levels, you will need pull ups on both sides.  It is theoretically possible to operate with pull ups on one side as long as you are not trying to translate voltage levels but our applications engineer for out I2C switches like TCA9545A told me that we do not show any application notes or datasheets with pull ups only on one side.

    Thank you,

    Adam  

  • 0 in reply to Adam Torma
    Guru 27585 points

    Adam san,

    Thank you for your reply.
    We got that heoretically possible to operate with pull ups on one side in case of no translating voltage levels.
    However, we will recommend our customer to insert pull ups to both sides.

    kind regard,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    Guru 27585 points

    Adam san,

    We have additional question.
    Please refer to following file;

    2844.20141006_DVI_TS3V642.pdf

    About "1. Master- Slave(unfixed)", voltage and value of pull ups are different.
    So, at Display monitor side, is it required to change value of pull ups, isn't it?
    If you have some idea, please let know us.

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 45575 points

    Hirotaka,

    The pullup resistors on each side of the device will be in parallel when the switch is on and they should follow the requirements below.  The pull ups are not required to be the same but one will have a stronger pull up than the other and have different performance.  This link discusses the effects of different pull up resistances have on an I2C clock.  http://www.dsscircuits.com/index.php/articles/47-effects-of-varying-i2c-pull-up-resistors 

    The minimum pull-up resistance Rp is a function of V+5V/+5V_DDC, VIL(max) and IIL: 

    Rp(min)= ((V+5V/+5V_DDC) - (VILmax)) / IIL

    The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL =400 kHz) and bus capacitance, Cb:

     Rp(max)= tr / (0.8473 x Cb) 

    The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the TS3DV642, COFF, the capacitance of wires/connections/traces, and the capacitance of each individual slave on a given channel. If multiple channels will be activated simultaneously, each of the slaves on all channels will contribute to total bus capacitance.

    Adam

  • 0 in reply to Adam Torma
    Guru 27585 points

    Adam san,

    Thank you for your updata!

    We got your saying.
    However, we'd like to confirm one point finally, on the schematic V+ and V+5v_DDC are different voltage(another power) and grounds.
    So, it is required to equalize ground levels(V+ and V+5v_DDC), isn't it?

    Kind regards,

    Hirotaka

  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 45575 points

    Hirotaka,

    No it is not required to have the the signal path ground equalized for our TS3DV642 to pass the signal through.  However, there may be some issues if your master and slaves are at different ground levels since the signals going across will not be referenced to the same potential.

    Adam  

  • 0 in reply to Adam Torma
    Guru 27585 points

    Adam san,

    Thank you for your prompt reply!

    Kind regards,

    Hirotaka Matsumoto