Asm errors after migrating from ccs3.3 to ccs5.1

Aadishri G S

Other Parts Discussed in Thread: CCSTUDIO

Hi,

I have migrated my project from ccs3.3 to ccs5.1. I am particularly unable to build some asm files. Below is one such error.

I*********************************************************************************

"D:/ROM/source/fpu/FS_MUL.asm", ERROR! at line 50:
 [E0002]
 Instruction is only available in V5 and higher
 CDP p5,#F_MUL,ResultReg0,SP_OP2,SP_OP1 ; Perform the Single Precision Multiplication

*********************************************************************************

I went through the instruction set in Reference manuals(thumb instruction set) which says

*********************************************************************************

Assembler syntax
CDP{2}<c><q> <coproc>, #<opc1>, <CRd>, <CRn>, <CRm> {,#<opc2>}
where:
2 If specified, selects the C == 1 form of the encoding. If omitted, selects the C == 0 form.
<c><q> See Standard assembler syntax fields on page 4-6.
<coproc> Specifies the name of the coprocessor, and causes the corresponding coprocessor number to
be placed in the cp_num field of the instruction. The standard generic coprocessor names
are p0, p1, ..., p15.
<opc1> Is a coprocessor-specific opcode, in the range 0 to 15.
<CRd> Specifies the destination coprocessor register for the instruction.
<CRn> Specifies the coprocessor register that contains the first operand.
<CRm> Specifies the coprocessor register that contains the second operand.
<opc2> Is a coprocessor-specific opcode in the range 0 to 7. If it is omitted, <opc2> is assumed to
be 0.

*********************************************************************************

The usage does not seem to violate this.

I would like to know how to resolve this issue and what is meant by V5 in the message

 'Instruction is only available in V5 and higher'

Also, has the ARM syntax changed from ccs3.3 to ccs5.1 in some cases?

 Is there no compatibility module which can compile the ccs3.3 code itself in ccs5.1.

Regards,

Aadishri

over 13 years ago

0 AartiG over 13 years ago

TI__Guru**** 173310 points

Aadishri G S said:

 'Instruction is only available in V5 and higher'

This message is saying that the instruction syntax is supported only in ARM v5 architecture and higher. Please take a look at slide 3 of this presentation for correlating architecture versions with processors.

Over time, the ARM codegen tools have evolved to add support for the different ABIs and ARM architectures, Starting with codegen tools 4.1.x the default ABI also changed from the older TIABI to TI ARM9 ABI. If you have the latest version of CCS 3.3, you will find ARM codegen tools v4.1.4 in it. You can review the CGTNew.txt file within the C:\CCStudio_v3.3\tms470\docs folder to understand the ABI changes that came starting with that veraion. If you are migrating code from an older version of compiler tools (that came with CCS 3.3) to a newer version (that comes with CCS v5) these are some of the factors to consider.

Which version of compiler tools did you use when building with CCS 3.3? You can check by going to the Component Manager, Build Tools and check the version of TMS470 code generation tools. To perform the migration in a more step-by-step approach you could first start off by setting CCSv5 to use the same version of compiler tools as you did with CCS 3.3. This page describes how to do that: http://processors.wiki.ti.com/index.php/Compiler_Installation_and_Selection#CCStudio_5.1
Verify that the project builds and works as expected. Then modify the project to use the newer version of compiler tools. You may need to set/keep some compiler options to maintain backward compatibility and/or modify code to make it compatible with the newer tools.

0 Aadishri G S over 13 years ago in reply to AartiG

Intellectual 505 points

Dear AartiG,

As per your suggestion, I compiled with earlier ccd 3.3 cgtools(4.1.4). The files compiled. Thank you.

But if I change to compile with cg tools 4.9.0(Project->Properties->CCS General->Code-generation tools),

the abi option((Project->Properties->CCS Build->TMS470 Compiler->Runtime Model Options->abi) automatically changes to ti_arm9_abi.

Even if I change to tiabi, I get the same error,

**********************************************************************************************************************

Instruction is only available in V5 and higher
 CDP p5,#F_SUB,ResultReg0,SP_OP2,SP_OP1 ; Perform the Single Precision Substraction

**********************************************************************************************************************

I checked this presentation. Here, in slide, 'ARM Processors Overview', it says

ARM7  |       ARMv4T  |      -mv4 
ARM9  |    ARMv5TE  |     -mv5e

I am using '-mv4' option itself.

I am unable to understand whether I have to change some other compile option or make the change in the instruction.

I am skeptical about the latter as I am still using '-mv4' option and the same instruction ran with '-mv4 -tiabi ' options in cgtools 4.1.4 and it compiles.

Please help me resolve this.

Regards,

Aadishri

0 AartiG over 13 years ago in reply to Aadishri G S

TI__Guru**** 173310 points

It may be that the instruction may need to be changed. Could you attach the assembly file which generates this error and the full list of compiler options you are using?

0 Aadishri G S over 13 years ago in reply to AartiG

Intellectual 505 points

Hi AartiG,

Please find the compile options I am using:

"-mv4 -g --define="_DEBUG" --include_path="C:/ccs/ccsv5/tools/compiler/tms470/include" --include_path="/packages/ti/xdais" --diag_warning=225 -me --abi=tiabi --code_state=16 --std_lib_func_redefined --obj_directory="C:/GNSS_45nm/Private/source/product/ti/GPS_ROM/projectfiles/fpu/Build_45NM""

I have attached one of the asm files(renamed as .txt) which throws this error. The CDP instruction is used in line 47 and 61.

Below are the ccs 3.3 compiler options that I used:

-g -pdsw225 -ol0 -fr"C:\GNSS_45nm\Private\source\product\ti\GPS_ROM\projectfiles\fpu\Build_45NM" -d"_DEBUG" -me -mt -mv4 --abi=tiabi

Regards,

Aadishri

5516.PRI_SUB.asm.txt

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;******************************************************************************
;            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
;                                                                             
;   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
;   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
;   product  is  protected  under  copyright  law  and  trade  secret law as an 
;   unpublished work.  Created 2010, (C) Copyright 1997 Texas Instruments.  All 
;   rights reserved.                                                            
;                  
;                                                           
;   Filename        : pri32.asm
;
;   Description     : 32BIS compiled Coprocessor functions
;
;   Version number  : 1
;
;   Date        : 28/6/2010 
;
;
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

;******************************************************************************
;            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
;                                                                             
;   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
;   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
;   product  is  protected  under  copyright  law  and  trade  secret law as an 
;   unpublished work.  Created 2010, (C) Copyright 1997 Texas Instruments.  All 
;   rights reserved.                                                            
;                  
;                                                           
;   Filename       	: pri32.asm
;
;   Description    	: 32BIS compiled Coprocessor functions
;
;   Version number	: 1
;
;   Date 		: 28/6/2010 
;
;
;****************************************************************************
	.include pri.h

	.global	 	FS_ADD	 
	.global 	FS_SUB
	 .state32	
	.ref _pri_rts_redirection
m0	.set	r2
e0	.set	r3
m1	.set	r4
e1	.set	r5
shift	.set	r6
tmp	.set	lr

 
FS_ADD:  STMFD    SP!,{R5}  
	  LDR  R5, pri_rts_redirect
	  LDR  R5, [R5]
	  CMP  R5, #1
  	  LDMFD SP!,{R5}	  
          BNE  FS_ADD_rts
	  INT_LOCK
	  MOVE_OP_SP
	  CDP   p5,#F_ADD,ResultReg0,SP_OP2,SP_OP1  ; Perform the  Single Precision Addition
     	  MOVE_RESTOARM_SP
          INT_UNLOCK
	  BX lr


FS_SUB:  STMFD    SP!,{R5}   
	 LDR  R5, pri_rts_redirect
	 LDR  R5, [R5]
	 CMP  R5, #1
	 LDMFD SP!,{R5}
         BNE  FS_SUB_rts
 	 INT_LOCK
         MOVE_OP_SP
	 CDP   p5,#F_SUB,ResultReg0,SP_OP2,SP_OP1  ; Perform the Single Precision Substraction
         MOVE_RESTOARM_SP
         INT_UNLOCK
	 BX lr

pri_rts_redirect .word _pri_rts_redirection

FS_SUB_rts:	.asmfunc stack_usage(24)
	EOR	r1, r1, #0x80000000	; NEGATE INPUT #2

FS_ADD_rts:
	STMFD	sp!, {r2-r6, lr}

	MOV	m1, r1, LSL #8		; PUT INPUT #2 MANTISSA IN m1
	MOV	e1, r1, LSL #1		; PUT INPUT #2 EXPONENT IN e1
	MOVS	e1, e1, LSR #24		;
	BNE	$1			;

	CMP	m1, #0			; IF DENORMALIZED NUMBER (m0 != 0 AND
	MOVNE	r0, #0			; e1 == 0), THEN UNDERFLOW
	LDMFD	sp!, {r2-r6, pc}	; ELSE IT IS ZERO SO RETURN INPUT #1

$1:	ORR	m1, m1, #0x80000000	; SET IMPLIED ONE IN MANTISSA

	CMP	e1, #0xFF		; IF e1 == 0xFF, THEN OVERFLOW
	
	BEQ	ovfl1			;

	MOV	m1, m1, LSR #2		; ADJUST THE MANTISSA
	CMP	r1, #0			; IF INPUT #2 IS NEGATIVE,
	RSBMI	m1, m1, #0		;  THEN NEGATE THE MANTISSA
	
	MOV	m0, r0, LSL #8		; PUT INPUT #1 MANTISSA IN m0
	MOV	e0, r0, LSL #1		; PUT INPUT #1 EXPONENT IN e0
	MOVS	e0, e0, LSR #24		;
	BNE	$2			;

	CMP	m0, #0			; IF DENORMALIZED NUMBER (m0 != 0 AND
	MOVNE	r0, #0			; e0 == 0), THEN UNDERFLOW
	MOVEQ	r0, r1			; ELSE IT IS ZERO SO RETURN INPUT #2
	LDMFD	sp!, {r2-r6, pc}	;

$2:	ORR	m0, m0, #0x80000000	; SET IMPLIED ONE IN MANTISSA

	CMP	e0, #0xFF		; IF e0 == 0xFF, THEN OVERFLOW
	BEQ	ovfl0			;

	MOV	m0, m0, LSR #2		; ADJUST THE MANTISSA
	CMP	r0, #0			; IF INPUT #1 IS NEGATIVE,
	RSBMI	m0, m0, #0		;  THEN NEGATE THE MANTISSA
	
	SUBS	shift, e0, e1		; GET THE SHIFT AMOUNT
	MOVMI	tmp, m0			; IF THE SHIFT AMOUNT IS NEGATIVE, THEN
	MOVMI	m0, m1			;  SWAP THE TWO MANTISSA SO THAT m0
	MOVMI	m1, tmp			;  CONTAINS THE LARGER VALUE,
	RSBMI	shift, shift, #0	;  AND NEGATE THE SHIFT AMOUNT,
	MOVMI	e0, e1			;  AND ENSURE THE LARGER EXP. IS IN e0

	CMP	shift, #30		; IF THE 2nd MANTISSA IS SIGNIFICANT,
	ADDMI	m0, m0, m1, ASR shift	; ADD IT TO THE FIRST MANTISSA
	CMP	m0, #0x0		;
	MOVEQ	r0, #0			; IF THE RESULT IS ZERO, 
	LDMEQFD	sp!, {r2-r6, pc}	;  THEN UNDERFLOW
	RSBMI	m0, m0, #0x0		; IF THE RESULT IS NEGATIVE, THEN
	MOVMI	tmp, #0x1		;  NEGATE THE RESULT AND
	MOVPL	tmp, #0x0		; NOTE THE SIGN

loop:	MOVS	m0, m0, LSL #1		; NORMALIZE THE RESULTING MANTISSA
	SUB	e0, e0, #1		; ADJUSTING THE EXPONENT AS NECESSARY
	BPL	loop			;

	ADDS	m0, m0, #0x80		; ROUND THE MANTISSA TO THE NEAREST
	ADDCS	e0, e0, #1		; ADJUST EXPONENT IF AN OVERFLOW OCCURS
	MOVCC	m0, m0, LSL #1		; REMOVE THE IMPLIED ONE

	ADDS	e0, e0, #2		; NORMALIZE THE EXPONENT
	MOVLE	r0, #0			; CHECK FOR UNDERFLOW
	LDMLEFD	sp!, {r2-r6, pc}	;
	CMP	e0, #0xFF		; CHECK FOR OVERFLOW
	BCS	ovfl			;

	MOV	r0, m0, LSR #9		; REPACK THE MANTISSA INTO r0
	ORR	r0, r0, e0, LSL #23	; REPACK THE EXPONENT INTO r0
	ORR	r0, r0, tmp, LSL #31	; REPACK THE SIGN INTO r0

	LDMFD	sp!, {r2-r6, pc}	;
	
ovfl1:	MOV	r0, r1			; OVERFLOW
ovfl0:  MOV	tmp, r0, LSR #31	;
ovfl:	MOV	tmp, tmp, LSL #31	; ISOLATE SIGN BIT
	MOV	r0, #0xFF		; SET UP Emax EXPONENT
	MOV	r0, r0, LSL #23
	ORR	r0, r0, tmp		; COMBINE SIGN AND EXPONENT
	LDMFD	sp!, {r2-r6, pc}	;

0 AartiG over 13 years ago in reply to Aadishri G S

TI__Guru**** 173310 points

I am missing the include file pri.h hence cannot compile the file successfully. However, even with all the other assembler errors generated I don't see the "Instruction is only available in V5 and higher " error with CGT 4.9.0. If you can include the pri.h and any other files that file may include so I can get a successful compile, I can confirm if I can reproduce the error or not.

0 Aadishri G S over 13 years ago in reply to AartiG

Intellectual 505 points

Dear AartiG,

Please find the header file attached.

Regards,

Aadishri

0 AartiG over 13 years ago in reply to Aadishri G S

TI__Guru**** 173310 points

Sorry, but there was no file attached.

0 Aadishri G S over 13 years ago in reply to AartiG

Intellectual 505 points

Hi AarthiG,

Sorry too! Please find the same attached

2627.PRI.h.txt

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;******************************************************************************
;            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
;                                                                             
;   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
;   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
;   product  is  protected  under  copyright  law  and  trade  secret law as an 
;   unpublished work.  Created 2010, (C) Copyright 1997 Texas Instruments.  All 
;   rights reserved.                                                            
;                  
;                                                           
;   Filename        : pri.h
;
;   Description     : pri coprocessor header file 
;
;   Version number  : 1
;
;   Date        : 28/6/2010 
;
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

;******************************************************************************
;            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
;                                                                             
;   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
;   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
;   product  is  protected  under  copyright  law  and  trade  secret law as an 
;   unpublished work.  Created 2010, (C) Copyright 1997 Texas Instruments.  All 
;   rights reserved.                                                            
;                  
;                                                           
;   Filename       	: pri.h
;
;   Description    	: pri coprocessor header file 

;
;   Version number	: 1
;
;   Date 		: 28/6/2010 
;
;
;*************************************************************************
; Operation code are assumed as follows


INT_LOCK_MSK        .equ     0x000000C0              ; Interrupt lockout mask value


INFO_SP     .equ   0        ; Used for Single Precision operation
INFO_DP     .equ   1        ; Used for Double Precision operation

NO_OP	    .equ   0        ; No operation
F_ADD       .equ   1        ; Addition 
F_SUB       .equ   2        ; Substraction
F_MUL       .equ   3        ; Multiplication
F_DIV       .equ   4        ; Division
F_DADD      .equ   1        ;Double precision Addition
F_DSUB      .equ   2        ;Double precision Substraction
F_DMUL      .equ   3        ;Double precision Mulitplication
F_DDIV      .equ   4        ;Double precision Division
F_CMP       .equ   5        ;Single precision Comparison
F_DCMP      .equ   5        ;Double precision Comparion


ResultReg0    .equ     C4
ResultReg1    .equ     C5 
SP_OP1        .equ     C0
SP_OP2        .equ     C1
DP_OP1        .equ     C0
DP_OP2        .equ     C2
CPSR_FLAG_MSK .equ     0x000000FF

CLEAR_UIDFLAG_MSK   .equ     0xF0000000 

      .state32

;*********************MACROS FOR Transfer of Operands From /To ARM/CO_OP***********************
MOVE_OP_SP .macro   ;Move the operands for Single precision operation to CO_OP registers
           MCRAL p5,#NO_OP,R0,C0,C0    ;Move R0->CP0
           MCRAL p5,#NO_OP,R1,C1,C1    ;Move R1->CP1
           .endm

MOVE_OP_DP .macro ; Move the operands for Double precision operation to CO_OP registers
            MCRAL p5,#NO_OP,R0,C1,C1    ;Move R0->CP1
            MCRAL p5,#NO_OP,R1,C0,C0    ;Move R1->CP0
            MCRAL p5,#NO_OP,R2,C3,C3    ;Move R2->CP3
            MCRAL p5,#NO_OP,R3,C2,C2    ;Move R3->CP2
            .endm

MOVE_RESTOARM_SP .macro ; transfer the Single precision operation result to ARM regsiter macro
                  MRCAL p5,#NO_OP,R0,ResultReg0,ResultReg0  ; Transfer the result , ARM register R0
                 .endm


MOVE_RESTOARM_DP .macro  ; transfer the Double precision operation result to ARM regsiter macro
                  MRCAL p5,#NO_OP,R0,ResultReg1,ResultReg1  ; Transfer the result , ARM register R0
                  MRCAL p5,#NO_OP,R1,ResultReg0,ResultReg0  ; Transfer the result , ARM register R1
                  .endm
;**************************************************************************************************
INT_LOCK  .macro    ; Lock the interupts during pri instruction execution
           STMFD    SP!,{R7-R8}                    ;Save the R8 onto Stack  
           MRS   R8,CPSR                        ;Save the CPSR in R8
           MOV   R7,R8
           ORR  R7, R7,#INT_LOCK_MSK
           MSR   CPSR,R7          ;Setup the new CPSR with FIQ and IRQ disable
          .endm 
	   
INT_UNLOCK    .macro
               MSR CPSR,R8
               LDMFD SP!,{R7-R8}
               .endm 
 
INT_LOCK_CMP  .macro    ; Lock the interupts during pri instruction execution
           STMFD    SP!,{R6,R7,R8}                        ;Save the CPSR onto stack
           MRS      R7,CPSR                        ;Save the CPSR in R8
           MOV      R8,R7
           ORR      R8, R8,#INT_LOCK_MSK
	   MSR      CPSR,R8          ;Setup the new CPSR with FIQ and IRQ disable
          .endm

CPSR_RESTORE_CMP   .macro                         ; For compare intruction the N,Z,C & V flag need to be taken care of
                   MRCAL p5,#NO_OP,R6,C8,C8       ;Transfer the C8 contents to register R6
	           AND   R6,R6,#CLEAR_UIDFLAG_MSK ;Clear the 27,26 and 25th bit if was set due to CDP operation
  	           AND   R7,R7,#CPSR_FLAG_MSK      ;Clear the N,Z,C and V flags bits  
		   ORR   R6,R6,R7                  ;Restore the CPSR regsiter contents excpet the N,Z,C and V flag 
	           MSR   CPSR,R6                       ;Setup the new CPSR
                    LDMFD SP!,{ R6,R7,R8}
	           .endm

Regards,

Aadishri

0 AartiG over 13 years ago in reply to Aadishri G S

TI__Guru**** 173310 points

Thanks for providing the file. I can reproduce the error you mentioned. I see that there is no error with CGT 4.1.x but starting with 4.4.0, all the later compiler versions generate the error. I will see if I can get someone else to comment on the reason for this.

0 Aadishri G S over 13 years ago in reply to AartiG

Intellectual 505 points

can you please update me...

0 ThomasS over 13 years ago in reply to Aadishri G S

TI__Expert 6550 points

The CDP and CDP2 instructions are only available for Thumb-2 devices. I read the thread too quickly. This appears to be a bug. It looks like we took the warning for the CDP2 instruction (available for v5 and higher) and applied it to CDP.

0 ThomasS over 13 years ago in reply to ThomasS

TI__Expert 6550 points

This issue is now in our bug tracking system as SDSCM00043069. The only workaround would be to assemble with version v5e or higher.

0 Aadishri G S over 13 years ago in reply to ThomasS

Intellectual 505 points

How can I check if the issue SDSCM00043069 is resolved?

Regards,

Aadishri

0 Archaeologist over 13 years ago in reply to Aadishri G S

TI__Guru* 84225 points

As indicated in the signatures of both Aarti and Thomas, you can track the status of known bugs by using SDOWP

0 Aadishri G S over 13 years ago in reply to ThomasS

Intellectual 505 points

Team,

Thank you for thr resolution.

Please let me know if I have to re-install CCSv5 or a version update will suffice to get the bug-free version.

Regards,

Aadishri

0 AartiG over 13 years ago in reply to Aadishri G S

TI__Guru**** 173310 points

Aadishri G S said:

Please let me know if I have to re-install CCSv5 or a version update will suffice to get the bug-free version.

If you are using CCS 5.1, you can simply download and install the latest ARM compiler tools v4.9.5 through the CCS update site. Go to CCS menu Help->Check for Updates and you can select the latest ARM CGT from there.

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Asm errors after migrating from ccs3.3 to ccs5.1