CGTOOL 7.3.2 created overlap sections

8360.Linker_Bug_Example.zip

2185.Linker_Bug_Example_map.zip

This is an issue report for a customer.

I am using the latest CGtools available (7.3.2) on Windows 7 64-bit, with the target processor being 6678 (--mv6600). The issue I am seeing is overlapping output sections when the -O3 option is used. More specifically, it seems that the linker will use a “hole” area created in one section, as a valid area for another section. This seems to have no effect when loading the result executable via JTAG, but the “hex6x” utility generates a warning and creates an invalid hex output file, which causes problems when booting via other methods.

 I have attached a minimal example project, created in CCS 5.1. It performs no useful function (don’t run it) but it demonstrates the problem.

 To reproduce, open the project in CCS. I assume you have a platform configuration with memory sections named “L2SRAM” and “DDR3”. If not, change the .cfg file accordingly. (If you do so, leave “my_task_code” and “my_task_data” together in a memory section separate from the others.)

 Build the project in Release mode. I have configured the project to run hex6x as a post-build action, so you should see a warning like this, as part of hex6x’s output:

 warning: section Linker_Bug_Example.out(my_task_data) at 0800030h overlaps

   "Linker_Bug_Example.out"   ==> my_task_code

   Linker_Bug_Example.out(my_task_code) (Linker_Bug_Example.out(my_task_data)

   incomplete or skipped)

 View the map file, and you will see that the “my_task_code” and “my_task_data” sections overlap by 10h bytes.

Attaching the project and map file zipped. 

**** Build of configuration Release for project Linker_Bug_Example ****

C:\ti\ccsv5\utils\bin\gmake -k all

'Building file: ../Linker_Bug_Example.cfg'

'Invoking: XDCtools'

"C:/ti/xdctools_3_22_04_46/xs" --xdcpath="C:/ti/bios_6_32_05_54/packages;C:/Program Files/Texas Instruments/pdk_C6678_1_0_0_17/packages;C:/DATA/Project/myBoard;" xdc.tools.configuro -o configPkg -t ti.targets.elf.C66 -p ti.platforms.evm6678 -r release -c "C:/ti/ccsv5/tools/compiler/c6000" "../Linker_Bug_Example.cfg"

making package.mak (because of package.bld) ...

generating interfaces for package configPkg (because package/package.xdc.inc is older than package.xdc) ...

configuring Linker_Bug_Example.xe66 from package/cfg/Linker_Bug_Example_pe66.cfg ...

cle66 package/cfg/Linker_Bug_Example_pe66.c ...

'Finished building: ../Linker_Bug_Example.cfg'

' '

'Building file: ../main.c'

'Invoking: C6000 Compiler'

"C:/ti/ccsv5/tools/compiler/c6000/bin/cl6x" -mv6600 -O3 --fp_mode=relaxed --include_path="C:/ti/ccsv5/tools/compiler/c6000/include" --display_error_number --diag_warning=225 --abi=eabi --opt_for_speed=5 --preproc_with_compile --preproc_dependency="main.pp" --cmd_file="./configPkg/compiler.opt" "../main.c"

'Finished building: ../main.c'

' '

'Building target: Linker_Bug_Example.out'

'Invoking: C6000 Linker'

"C:/ti/ccsv5/tools/compiler/c6000/bin/cl6x" -mv6600 -O3 --fp_mode=relaxed --display_error_number --diag_warning=225 --abi=eabi --opt_for_speed=5 -z -m"Linker_Bug_Example.map" --warn_sections -i"C:/ti/ccsv5/tools/compiler/c6000/lib" -i"C:/ti/ccsv5/tools/compiler/c6000/include" --reread_libs --rom_model -o "Linker_Bug_Example.out" -l"./configPkg/linker.cmd" "./main.obj" -l"libc.a"

<Linking>

'Finished building target: Linker_Bug_Example.out'

' '

C:/ti/ccsv5/utils/bin/gmake --no-print-directory post-build

'Create flash image: Intel-HEX'

"C:/ti/ccsv5/tools/compiler/c6000/bin/hex6x.exe" -i "Linker_Bug_Example.out" -o "Linker_Bug_Example.hex" -memwidth=8 -romwidth=8

Translating to Intel format...

"Linker_Bug_Example.out" ==> my_task_code

"Linker_Bug_Example.out" ==> my_task_data

"Linker_Bug_Example.out" ==> .text

"Linker_Bug_Example.out" ==> .const

"Linker_Bug_Example.out" ==> .vecs

"Linker_Bug_Example.out" ==> .cinit

warning: section Linker_Bug_Example.out(my_task_data) at 0800030h overlaps

Linker_Bug_Example.out(my_task_code) (Linker_Bug_Example.out(my_task_data)

incomplete or skipped)

' '

**** Build Finished ****