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In CSS 5.2.0.00069 I discover an issue, I don't know if is reported.
On this case:
HWREG(SOC_CM_DPLL_REGS + CM_DPLL_CLKSEL_TIMER7_CLK) &=
~(CM_DPLL_CLKSEL_TIMER7_CLK_CLKSEL);
HWREG(SOC_CM_DPLL_REGS + CM_DPLL_CLKSEL_TIMER7_CLK) |=
CM_DPLL_CLKSEL_TIMER7_CLK_CLKSEL_CLK_M_OSC;
When I compile with optimization level 4, the compiler collapse this two lines in one read write of the register, even if these registers has a volatile register rule, this issue affects some of settings of the dmtimer from AM335X_StarterWare_02_00_00_06, in my case the sysdelay library.
In this case the clock for this timer is not setup.
To resolve this issue I add an asm line:
HWREG(SOC_CM_DPLL_REGS + CM_DPLL_CLKSEL_TIMER7_CLK) &=
~(CM_DPLL_CLKSEL_TIMER7_CLK_CLKSEL);
asm("_DMTimer7ModuleClkConfig_");
HWREG(SOC_CM_DPLL_REGS + CM_DPLL_CLKSEL_TIMER7_CLK) |=
CM_DPLL_CLKSEL_TIMER7_CLK_CLKSEL_CLK_M_OSC;
This asm line split this two lines for correct compilation.
This sounds like a compiler bug, but we need to reproduce this ourselves to be sure. Please submit a test case as described in the last part of the forum guidelines.
Thanks and regards,
-George
Good morning George.
At this moment I cannot reproduce the same issue, because the project hi evolved.
But approximate same issue is when I compile attached project with optimization level 4, the clock for Timer 7 is not applied or the settings for Timer7 clock is cleared by another clock settings for another module, the point is only the clock for Timer7 is affected, I don't now exactly where is the problem because on debugging I don't have a complete view of registry settings, like complete timer 7 registry settings.
When I compile the project with optimization level 3 everything is work fine.
Another problem is that, when I compile twice the same project after a complete clean with optimization 3 and 4, the code is not the same, on one compilation is faster that another, in same cases is twice faster than another.
I uploaded on one of my sites.
Best regards,
Iulian
Iulian Gheorghiu said:But approximate same issue is when I compile attached project with optimization level 4, the clock for Timer 7 is not applied or the settings for Timer7 clock is cleared by another clock settings for another module, the point is only the clock for Timer7 is affected, I don't now exactly where is the problem because on debugging I don't have a complete view of registry settings, like complete timer 7 registry settings.
I'm sorry, but there is nothing for me to go on here. I need something more specific.
Iulian Gheorghiu said:Another problem is that, when I compile twice the same project after a complete clean with optimization 3 and 4, the code is not the same, on one compilation is faster that another, in same cases is twice faster than another.
Are you talking about the amount of time it takes to compile the project? I presume so. I'm not sure what you are comparing. Tell me about exactly one build time comparison.
Thanks and regards,
-George
Good morning Georgem.
I have not bothered because I did not know how to explain the issue.
But I solved the problem.
The starter ware let the AINTC module unprotected, this generate all of this issues.
The issue is that when another module set up the interrupts somehow is cleared another setting from another interrupts already enabled, or something like that.(this issue is detected for example when I started the LWIP library after I set up the USB and Timer7, the USB and Timmer7 interrupts is turned off(the Timer is running but don't generate any interrupt, this is available and for USB )).
Example:
I protected the interrupt module, from:
static void AintcCPSWIntrSetUp(void)
{
/* Register the Receive ISR for Core 0 */
IntRegister(SYS_INT_3PGSWRXINT0, CPSWCore0RxIsr);
/* Register the Transmit ISR for Core 0 */
IntRegister(SYS_INT_3PGSWTXINT0, CPSWCore0TxIsr);
/* Set the priority */
IntPrioritySet(SYS_INT_3PGSWTXINT0, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntPrioritySet(SYS_INT_3PGSWRXINT0, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable the system interrupt */
IntSystemEnable(SYS_INT_3PGSWTXINT0);
IntSystemEnable(SYS_INT_3PGSWRXINT0);
}
to:
static void AintcCPSWIntrSetUp(void)
{
IntProtectionDisable();
/* Register the Receive ISR for Core 0 */
IntRegister(SYS_INT_3PGSWRXINT0, CPSWCore0RxIsr);
/* Register the Transmit ISR for Core 0 */
IntRegister(SYS_INT_3PGSWTXINT0, CPSWCore0TxIsr);
/* Set the priority */
IntPrioritySet(SYS_INT_3PGSWTXINT0, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntPrioritySet(SYS_INT_3PGSWRXINT0, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable the system interrupt */
IntSystemEnable(SYS_INT_3PGSWTXINT0);
IntSystemEnable(SYS_INT_3PGSWRXINT0);
IntProtectionEnable();
}
This changes I made for all set-ups of interrupts, and the issue has disappeared.
I disable the protection only when I change some settings in AINTC, after changes is made I enable protection.
About the execution program speed, the difference is from the ASM code generated by the compiler and runned with Cache OFF, the difference of speed between two compilation is more observable with Cache OFF, With Cache ON the difference between two executable can't be observed because the Data and Instruction traffic between cache and CPU is to faster to be observed the difference.
Thank you for all.
Best regards.