In CSS 5.2.0.00069 I discover an issue, I don't know if is reported.
On this case:
HWREG(SOC_CM_DPLL_REGS + CM_DPLL_CLKSEL_TIMER7_CLK) &=
~(CM_DPLL_CLKSEL_TIMER7_CLK_CLKSEL);
HWREG(SOC_CM_DPLL_REGS + CM_DPLL_CLKSEL_TIMER7_CLK) |=
CM_DPLL_CLKSEL_TIMER7_CLK_CLKSEL_CLK_M_OSC;
When I compile with optimization level 4, the compiler collapse this two lines in one read write of the register, even if these registers has a volatile register rule, this issue affects some of settings of the dmtimer from AM335X_StarterWare_02_00_00_06, in my case the sysdelay library.
In this case the clock for this timer is not setup.
To resolve this issue I add an asm line:
HWREG(SOC_CM_DPLL_REGS + CM_DPLL_CLKSEL_TIMER7_CLK) &=
~(CM_DPLL_CLKSEL_TIMER7_CLK_CLKSEL);
asm("_DMTimer7ModuleClkConfig_");
HWREG(SOC_CM_DPLL_REGS + CM_DPLL_CLKSEL_TIMER7_CLK) |=
CM_DPLL_CLKSEL_TIMER7_CLK_CLKSEL_CLK_M_OSC;
This asm line split this two lines for correct compilation.