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Register read not acting volatile. Optimization problem? Concerto, SYS/BIOS, C28 Core.

Hello,

I'm working on a routine that uses SPI to read from an FPGA, and the FPGA uses an IO pin to indicate that data is available.  

In my function, I read the state of that pin and continue reading until it goes low.  Unfortunately, my register-read does not change when the IO pin changes, unless I explicitly re-delcare the register struct as volatile inside the function.  The struct is already declared "extern volatile" in F28M35x_GPIO.h

   Int16 ReadCommPortBuffer( Uint16 NumWordsToGet, Uint16 *RecBuffer)
{
      extern volatile struct GPIOG1_DATA_REGS GpioG1DataRegs; // REGISTER STRUCT DOESN'T ACT VOLATILE WITHOUT THIS LINE.

while( GpioG1DataRegs.GPADAT.bit.GPIO9 == 1 ) // Read excess data from the FPGA
{...}
}
Re-declaring the struct outside the function (like at the top of the file, or explicitly including F28M35x_GPIO.h) does not work.
Could there be some optimization that is overriding the volatile parameter?  I don't want to need to re-declare these structs everywhere I use them because it 
destroys the hardware abstraction.
Thanks for any advice.
  • What compiler version are you using (not CCS version)?  What command-line options?

    If you move the "extra" declaration outside of the function to the global scope, does it still work?

    Could you show me the disassembly corresponding to this while loop?

    Could you preprpocess your file with -ppo and verify in the resulting .pp file that the declaration of GpioG1DataRegs in F28M35x_GPIO.h is visible before the definition of ReadCommPortBuffer?

  • I have a similar problem - volatile declaration doesn't work.

    I have two threads that share data by reading and writing from a global variable:

    extern volatile int32_t sample_counter;

    It works fine under Debug build, or Release build with the -o1 option. But it fails to update data if built as Release with -o2 option.

    It won't help even I declare it again within the function.

    Can anyone help?

    BR

    C.J.

  • By the way, the variable is located in the L1SRAM, so the cache coherence shouldn't be a problem. I am using ccs5.0.2.23, and 6678l.

  • We'll need a complete, compilable test case that demonstrates the problem, or we can't do anything.   Be sure to include the command line options used and the compiler version (not the CCS version).