Is it possible to simulate cycles and memory access latency? - C674x CPU Cycle Accurate Simulator

Hello Chris,

c0l0jar0 said:

Is it possible to use a cycle accurate simulator to profile the execution of our code and model the memory allocation and caching used on our final product?

Yes, but you need to make sure you use a device cycle accurate simulator (ex. C6747 Device Cycle Accurate Simulator), since those model cache. CPU simulators (like the C674x CPU Cycle Accurate Simulator) do not model cache and assume a flat memory system.

c0l0jar0 said:

If so, what steps do I need to take?

Make sure you use a Device Cycle Accurate Simulator as mentioned above, and not a CPU simulator.

c0l0jar0 said:

If not, what is the point in profiling if it is only half the picture?

Profiling on CPU simulators are useful for people writing codecs and such modeling the entire system is not as crucial. For people interested in the whole system, there isn't as much value as you alluded to.

c0l0jar0 said:

Do people use emulators for this purpose?

Yes

c0l0jar0 said:

You can't get profile information on an emulator, you have to do it by hand don't you?

There are some alternatives, like using the profile clock. If you have a device that supports trace, you have that option available also.

c0l0jar0 said:

Is it possible to write DSS scripts for this purpose?

You can use DSS to control the profile clock, read at various intervals and store the information.

Thanks

ki