CCSv5 profile clock usage

Hi HR,

have you seen this wiki?

http://processors.wiki.ti.com/index.php/Profile_clock_in_CCS

Best Regards,
Lisa

Hi Lisa,

Yes I have seen it but ... there are a lot of option's under clock setup like CPU.stall.mem.L1P, MSMC.program.read, and much more what are all those options ? how do I use them ?

Thanks,

HR

Hi HR,

could you send a screen capture?  I would like to ensure we are discussing the same thing here.

Best Regards,
Lisa

Hi Lisa,

Please find it attached,

Thanks,

HR4544.ClockSetup.pdf

Hi HR,

Are you asking how to utilize the values collected by the clock? Or are you simply asking what those events mean?

Thanks

ki

Hi Ki,

Both, as it is the first time I see this options,

Thanks,

HR

Hi Ki,

Yes this is the C6678, on HW there are a few more options which I don't see them in the Simulator Analysis Event Description page, is there an additional explanation?

Thanks,

HR

That wiki may be a bit dated. What are the other events?

Hi Ki,

There are a few other options like MARK Instructions 0,...3 and AEGEVT 1,...7, how does all of this works?

Thanks,

HR

HRi said:

MARK Instructions 0,...3

http://processors.wiki.ti.com/index.php/Advanced_Event_Triggering#Q:_What_does_the_.22MARK0_-_MARK3.22_mean.3F

HRi said:

AEGEVT 1,...7

http://processors.wiki.ti.com/index.php/Advanced_Event_Triggering#Q:_What_does_the_.22AEGEVT0_-_AEGEVT6.22.3F

Thanks

ki

Ki,

Thanks, but how does this connects to the clock setup? as it is set in a different place,

Thanks,

HR

HRi said:

Thanks, but how does this connects to the clock setup? as it is set in a different place,

All the clock does is count the number of times the event is triggered. It is just a counter and nothing more. Actual setup of the event is not related to the clock.

Not the events exposed to you are really relevant to be counted. I would just focus on the events that you wish to count instead of trying to understand how to use every event.

Ki,

Still is there any explanation how does it works for example counting the L1D cache miss and more...

Thanks,

Haim

Ki,

OK, Thank you very much,

HR