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EVMK2H Trouble Writing Memory Block

Other Parts Discussed in Thread: TCI6636K2H, TCI6638K2K

I have a problem that  i cant debug Hello.c in CCSv5 

My board is EVMK2H and target configuration is TCI6636K2H.ccxml 

MCSDK version is 3_00_03_15

I install many times and try 3_00_03_15 and 3_01_04_07 version.

Besides , i also try to install in windows and linux(Ubuntu 14.04),but both results are the same 

I show my console and GEL Output

console : 

C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: TCI6638K2K GEL file Ver is 1.4
C66xx_0: GEL Output: Detected PLL bypass disabled: SECCTL[BYPASS] = 0x00000000
C66xx_0: GEL Output: (3a) PLLCTL = 0x00000040
C66xx_0: GEL Output: (3b) PLLCTL = 0x00000040
C66xx_0: GEL Output: (3c) Delay...
C66xx_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F
C66xx_0: GEL Output: MAINPLLCTL0 = 0x07000000
C66xx_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000
C66xx_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040
C66xx_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000
C66xx_0: GEL Output: (7) SECCTL = 0x00090000
C66xx_0: GEL Output: (8a) Delay...
C66xx_0: GEL Output: PLL1_DIV3 = 0x00008002
C66xx_0: GEL Output: PLL1_DIV4 = 0x00008004
C66xx_0: GEL Output: PLL1_DIV7 = 0x00000000
C66xx_0: GEL Output: (8d/e) Delay...
C66xx_0: GEL Output: (10) Delay...
C66xx_0: GEL Output: (12) Delay...
C66xx_0: GEL Output: (13) SECCTL = 0x00090000
C66xx_0: GEL Output: (Delay...
C66xx_0: GEL Output: (Delay...
C66xx_0: GEL Output: (14) PLLCTL = 0x00000041
C66xx_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):
C66xx_0: GEL Output: PLL has been configured (122.88 MHz * 16 / 1 / 2 = 983.04 MHz)
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=2, md=9!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=25!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=26!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=18, md=27!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=19, md=28!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=19, md=29!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=30!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=31!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=32!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=33!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=21, md=34!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=22, md=35!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=22, md=36!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=23, md=37!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=23, md=38!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=39!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=40!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=41!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=42!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=43!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=44!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=45!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=46!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=26, md=47!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=27, md=48!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: WARNING: SYSCLK is the input to the PA PLL.
C66xx_0: GEL Output: Completed PA PLL Setup
C66xx_0: GEL Output: PAPLLCTL0 - before: 0x0x07080400 after: 0x0x07080400
C66xx_0: GEL Output: PAPLLCTL1 - before: 0x0x00002040 after: 0x0x00002040
C66xx_0: GEL Output: DDR begin
C66xx_0: GEL Output: XMC setup complete.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.
C66xx_0: GEL Output: DDR3A initialization complete
C66xx_0: GEL Output: DDR3 PLL Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3B clock now running at 800MHz.
C66xx_0: GEL Output: DDR3B initialization complete
C66xx_0: GEL Output: DDR done
C66xx_0: Trouble Writing Memory Block at 0xa020 on Page 0 of Length 0x13e: (Error -1190 @ 0x20) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.232.0)
C66xx_0: GEL: File:

Can someone tell a little bit  how to solve this bug ? Thanks

  • Hi,

    I don't have the same board as you, but errors such as the one above are directly related to either the Hardware or a mismatch between the GEL file selected and the board revision you have. In other words, both CCS and the JTAG debugger seem to be working absolutely fine.

    To help with the first scenario I would strongly suggest to check the board documentation for boot modes. At first I would set the board to boot their self demonstration mode so I would be sure the board, the device and the memory are fully functional. After that I would check the documentation to force the board to refrain from booting any pre-existing demo code - this is useful to prevent any pre-existing code from negatively influencing the hardware initialization routine performed by the GEL file (which is where the errors are coming from).

    If that does not help, I would suspect the GEL files are not tailored for the board revision you have. In this case, I would check with the experts in the device forum to see if they have specific details regarding the timeout errors you are experiencing.

    Hope this helps,
    Rafael
  • Hi

    I solved this problem by the website e2e.ti.com/.../394432

    But,i encountered another problem . I post my screen figure below 

     

    The debug process is hanged and i click c_int00 in DSP core C66XX_0.

    And then, it show the result: Can't find a source file at "/tmp/TI_MKLIBNvcmIk/SRC/boot.c" Locate the file or edit the source lookup path to include its location

  • Hi,

    For that last issue, please check:
    e2e.ti.com/.../1817351

    Regards,
    Rafael
  • HI, 

    Thanks for your help 

    I have solved this problem .