RTOS/TMDSEVM6678: TMS320C6678

Oh, I'm using CCS version 6.1.2.00015

Hi David,

I've forwarded this to the SW experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

David,

Can you share the map file for the application after the BIOS configuration was added. Also are you loading code in DDR in both BIOS and non-BIOS usecase. I would check for the entry point of the BIOS application and see if it not aligned to a 16 byte boundary.

what utility are you using to flash the NOR, does it have any restrictions on how big the size of the binary.

Regards,
Rahul

No, I am trying to run from L2SRAM.  Our H/W guys, in their infinite wisdom, decided we didn't need an stinking DDR so we won't have any on our production board.   The Linker.cmd file points everything to L2SRAM.   Could something in BIOS be trying to run from DDR and it's not being initialized?   I took a look at the .map file and it doesn't appear so to me.  But if I can figure out how to attach it I will.  I'm using the norwriter_evmc6678l program (slightly modified).  I don't think it is having a problem writing the image to Flash since it reads it back and verifies it.  I suppose I could write some code to read it from Flash and verify it myself against the image on disk.  Okay, I think I uploaded the file but it looks kinda goofy.  Let me know if I did it wrong and if so, how to do it correctly!

SWIT_Bootloader.zip

David,

No, it looks like your map file indicates DDR or MSMC regions are not being used and if the flash writer indicates that it flashed the image.
when the boot fails, have connected an emulator to see if the DSP core is hung in the ROM memory or if it is L2 ? We provide a Debug GEL for this device which you can use to see the device state and look at ROM boot loader state and errors. Could you run this GEL script after the boot fails to load your SYSBIOS app and report the log.
processors.wiki.ti.com/.../Keystone_Device_Architecture

Also, make sure the .rmd file that you use to convert the .out to .hex/.bin doesn`t need to be updated to account for the increased size.

Regards,
Rahul

Which script from that GEL file do you want me to run? There are over 100 of them! When I connected, the target is at address 0x20b00000. Here are a few of the scripts I ran:


C6678 Device Level Status-> C6678_Boot_Status:

C66xx_0: GEL Output: BOOTPROGRESS[31:0] ---> 0xA8014000
C66xx_0: GEL Output: BOOTCFG_BOOTCOMPLETE ---> 0x00000001

C66xx_0: GEL Output: C6678 Core 0 ---> Boot process Completed
C66xx_0: GEL Output: C6678 Core 1 ---> Boot in process. Not Complete
C66xx_0: GEL Output: C6678 Core 2 ---> Boot in process. Not Complete
C66xx_0: GEL Output: C6678 Core 3 ---> Boot in process. Not Complete
C66xx_0: GEL Output: C6678 Core 4 ---> Boot in process. Not Complete
C66xx_0: GEL Output: C6678 Core 5 ---> Boot in process. Not Complete
C66xx_0: GEL Output: C6678 Core 6 ---> Boot in process. Not Complete
C66xx_0: GEL Output: C6678 Core 7 ---> Boot in process. Not Complete


C6678 Device Level Status-> C6678_Reset_Status:

C66xx_0: GEL Output: BOOTCFG_RESET_STAT ---> 0x80000000

C66xx_0: GEL Output: C6678 Global Reset ---> Device received a global reset
C66xx_0: GEL Output: C6678 Core 0 Reset ---> Core 0 has not received a local reset
C66xx_0: GEL Output: C6678 Core 1 Reset ---> Core 1 has not received a local reset
C66xx_0: GEL Output: C6678 Core 2 Reset ---> Core 2 has not received a local reset
C66xx_0: GEL Output: C6678 Core 3 Reset ---> Core 3 has not received a local reset
C66xx_0: GEL Output: C6678 Core 4 Reset ---> Core 4 has not received a local reset
C66xx_0: GEL Output: C6678 Core 5 Reset ---> Core 5 has not received a local reset
C66xx_0: GEL Output: C6678 Core 6 Reset ---> Core 6 has not received a local reset
C66xx_0: GEL Output: C6678 Core 7 Reset ---> Core 7 has not received a local reset


C6678 APIs-> Device_Config_State_Snapshot:

C66xx_0: GEL Output: *******************************************************************************************************
C66xx_0: GEL Output: ********************************** C6678 BOOTSTRAP CONFIGURATION ******************************************************
C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: ********************************** C6678 Device Status Register (DEVSTAT) ************************************

C66xx_0: GEL Output: BOOTCFG_DEVSTAT ---> 0x0000080B

C66xx_0: GEL Output: LENDIAN[0] ---> Little Endian
C66xx_0: GEL Output: BOOTMODE[3:1] ---> I2C Boot Mode
C66xx_0: GEL Output: SmartReflex ID[5:4] ---> 0
C66xx_0: GEL Output: MODE[10] ---> Master Mode
C66xx_0: GEL Output: ADDRESS[11] ---> Boot From I2C EEPROM at I2C bus address 0x51
C66xx_0: GEL Output: SPEED[12] ---> I2C data rate set to approximately 20 kHz
C66xx_0: GEL Output: PARAMETER IDX[9:4] ---> 0
C66xx_0: GEL Output: PCIESSEN[16] ---> Initial state of the power domain and the clock domain for PCIE subsystem is Disabled
C66xx_0: GEL Output: PCIESSMODE[15:14] ---> PCIE in End-point mode
C66xx_0: GEL Output: PASSCLKSEL[17] ---> SYSCLK / ALTCORECLK (controlled by CORECLKSEL pin) is used as the input to PA_SS PLL
C66xx_0: GEL Output: SYSCLKOUTEN[0] ---> No Clock Output

C66xx_0: GEL Output: ********************************** C6678 DIEID Register (DIEID) ************************************

C66xx_0: GEL Output: DIEID0 ---> 0x0100600D
C66xx_0: GEL Output: DIEID1 ---> 0x0403E91A
C66xx_0: GEL Output: DIEID2 ---> 0x00000000
C66xx_0: GEL Output: DIEID3 ---> 0x00660021
C66xx_0: GEL Output: ********************************** C6678 MACID Register (MACID) ************************************

C66xx_0: GEL Output: MACID[31:0] ---> 0xEAD491BB
C66xx_0: GEL Output: MACID[32:47] ---> 0x0017
C66xx_0: GEL Output: BCAST[16](Broadcast Reception) ---> Broadcast
C66xx_0: GEL Output: BCAST[17](MAC Flow Control) ---> Off
C66xx_0: GEL Output: CHECKSUM[24:31] ---> 0xBF

C66xx_0: GEL Output: *******************************************************************************************************
C66xx_0: GEL Output: ********************************** C6678 MASTER VBUSM PRIORITY CONFIGURATION **********************************
C66xx_0: GEL Output: ************************************PRIORITY-0 (Highest) & PRIORITY-7 (Lowest)********************************

C66xx_0: GEL Output: EDMA0_TC0 Master: Priority-0
C66xx_0: GEL Output: EDMA0_TC1 Master: Priority-0

C66xx_0: GEL Output: EDMA1_TC0 Master: Priority-0
C66xx_0: GEL Output: EDMA1_TC1 Master: Priority-0
C66xx_0: GEL Output: EDMA1_TC2 Master: Priority-0
C66xx_0: GEL Output: EDMA1_TC3 Master: Priority-0

C66xx_0: GEL Output: EDMA2_TC0 Master: Priority-0
C66xx_0: GEL Output: EDMA2_TC1 Master: Priority-0
C66xx_0: GEL Output: EDMA2_TC2 Master: Priority-0
C66xx_0: GEL Output: EDMA2_TC3 Master: Priority-0

C66xx_0: GEL Output: PA PKT DMA Master: TX Priority-0, RX Priority-0

C66xx_0: GEL Output: SRIO PKT DMA Master: TX Priority-0, RX Priority-0

C66xx_0: GEL Output: QMSS PKT DMA Master: TX Priority-0, RX Priority-0

C66xx_0: GEL Output: QM_Second Master: Priority-0

C66xx_0: GEL Output: SRIO Master: Priority-0

C66xx_0: GEL Output: PCIE Master: Priority-0

C66xx_0: GEL Output: HYPERBRIDGE Master: Priority at VBUSM is determined according to the priority field value
C66xx_0: GEL Output: received from the command word. The pri bit encoding is given below:
C66xx_0: GEL Output: pri-0b0 ---> Priority0 on the VBUSM
C66xx_0: GEL Output: pri-0b1 ---> Priority4 on the VBUSM

C66xx_0: GEL Output: COREPAC0 MDMA Master(For other COREPACs load the GEL on the respective COREPAC): Urgent Priority-6, Normal Priority-7

C66xx_0: GEL Output: *************************** Voltage Control Identification Register (VCNTLID) ****************************

C66xx_0: GEL Output: PSC_VCNTLID ---> 0x0FBE0000

C66xx_0: GEL Output: SmartReflex Class-0 VCNTL selection coming from EFUSE(VCNTL) ---> 62
C66xx_0: GEL Output: Vdd corresponding to VCNTL#62: 1.097 Volts

C66xx_0: GEL Output: *******************************************************************************************************
C66xx_0: GEL Output: ********************************** C6678 PSC PWR DOMAINS STATUS **************************************
C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: Most peripheral logic (pwr domain) is in ##0N## state
C66xx_0: GEL Output: Per-core TETB and System TETB (pwr domain) is in **OFF** state
C66xx_0: GEL Output: Packet Coprocessor (pwr domain) is in **OFF** state
C66xx_0: GEL Output: PCIe (pwr domain) is in **OFF** state
C66xx_0: GEL Output: SRIO (pwr domain) is in **OFF** state
C66xx_0: GEL Output: HyperLink (pwr domain) is in **OFF** state
C66xx_0: GEL Output: MSMC RAM (pwr domain) is in ##0N## state
C66xx_0: GEL Output: C66x Core 0, L1/L2 RAMs (pwr domain) is in ##0N## state
C66xx_0: GEL Output: C66x Core 1, L1/L2 RAMs (pwr domain) is in ##0N## state
C66xx_0: GEL Output: C66x Core 2, L1/L2 RAMs (pwr domain) is in ##0N## state
C66xx_0: GEL Output: C66x Core 3, L1/L2 RAMs (pwr domain) is in ##0N## state
C66xx_0: GEL Output: C66x Core 4, L1/L2 RAMs (pwr domain) is in ##0N## state
C66xx_0: GEL Output: C66x Core 5, L1/L2 RAMs (pwr domain) is in ##0N## state
C66xx_0: GEL Output: C66x Core 6, L1/L2 RAMs (pwr domain) is in ##0N## state
C66xx_0: GEL Output: C66x Core 7, L1/L2 RAMs (pwr domain) is in ##0N## state
C66xx_0: GEL Output: *******************************************************************************************************
C66xx_0: GEL Output: ********************************** C6678 PSC CLOCK DOMAINS STATUS **************************************
C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: SHARED LPSC for all peripherals Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: SmartReflex Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: DDR3 EMIF Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: RESETISO[12] ---> RESET ISOLATION is ##Enabled##

C66xx_0: GEL Output: EMIF16-SPI Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: TSIP Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> **SwRstDisable** state
C66xx_0: GEL Output: MRST[10] ---> Module reset is **asserted**
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is **OFF**

C66xx_0: GEL Output: Debug Subsystem and Tracers Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> **SwRstDisable** state
C66xx_0: GEL Output: MRST[10] ---> Module reset is **asserted**
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is **OFF**

C66xx_0: GEL Output: Per-core TETB and System TETB Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> **SwRstDisable** state
C66xx_0: GEL Output: MRST[10] ---> Module reset is **asserted**
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is **OFF**

C66xx_0: GEL Output: RESETISO[12] ---> RESET ISOLATION is ##Enabled##

C66xx_0: GEL Output: Packet Accelerator Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> **SwRstDisable** state
C66xx_0: GEL Output: MRST[10] ---> Module reset is **asserted**
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is **OFF**

C66xx_0: GEL Output: Ethernet SGMIIs Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> **SwRstDisable** state
C66xx_0: GEL Output: MRST[10] ---> Module reset is **asserted**
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is **OFF**

C66xx_0: GEL Output: RESETISO[12] ---> RESET ISOLATION is ##Enabled##

C66xx_0: GEL Output: Security Accelerator Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> **SwRstDisable** state
C66xx_0: GEL Output: MRST[10] ---> Module reset is **asserted**
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is **OFF**

C66xx_0: GEL Output: PCIe Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> **SwRstDisable** state
C66xx_0: GEL Output: MRST[10] ---> Module reset is **asserted**
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is **OFF**

C66xx_0: GEL Output: SRIO Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> **SwRstDisable** state
C66xx_0: GEL Output: MRST[10] ---> Module reset is **asserted**
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is **OFF**

C66xx_0: GEL Output: RESETISO[12] ---> RESET ISOLATION is ##Enabled##

C66xx_0: GEL Output: HyperLink Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> **SwRstDisable** state
C66xx_0: GEL Output: MRST[10] ---> Module reset is **asserted**
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is **OFF**

C66xx_0: GEL Output: MSMC RAM Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: C66x Core 0 and Timer 0 Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[8] ---> Local reset is ##de-asserted##
C66xx_0: GEL Output: LRSTDONE[11] ---> Local reset is ##done##
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: C66x Core 1 and Timer 1 Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[8] ---> Local reset is ##de-asserted##
C66xx_0: GEL Output: LRSTDONE[11] ---> Local reset is ##done##
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: C66x Core 2 and Timer 2 Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[8] ---> Local reset is ##de-asserted##
C66xx_0: GEL Output: LRSTDONE[11] ---> Local reset is ##done##
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: C66x Core 3 and Timer 3 Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[8] ---> Local reset is ##de-asserted##
C66xx_0: GEL Output: LRSTDONE[11] ---> Local reset is ##done##
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: C66x Core 4 and Timer 4 Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[8] ---> Local reset is ##de-asserted##
C66xx_0: GEL Output: LRSTDONE[11] ---> Local reset is ##done##
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: C66x Core 5 and Timer 5 Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[8] ---> Local reset is ##de-asserted##
C66xx_0: GEL Output: LRSTDONE[11] ---> Local reset is ##done##
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: C66x Core 6 and Timer 6 Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[8] ---> Local reset is ##de-asserted##
C66xx_0: GEL Output: LRSTDONE[11] ---> Local reset is ##done##
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: C66x Core 7 and Timer 7 Clock domain Status:

C66xx_0: GEL Output: STATE[5:0] ---> ##Enable## state
C66xx_0: GEL Output: MRST[8] ---> Local reset is ##de-asserted##
C66xx_0: GEL Output: LRSTDONE[11] ---> Local reset is ##done##
C66xx_0: GEL Output: MRST[10] ---> Module reset is ##de-asserted##
C66xx_0: GEL Output: MRSTDONE[11] ---> Module reset is ##done##
C66xx_0: GEL Output: MCKOUT[12] ---> Module clock is ##ON##

C66xx_0: GEL Output: *******************************************************************************************************
C66xx_0: GEL Output: ********************************** C6678 BOOT STATUS ******************************************************
C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: BOOTPROGRESS[31:0] ---> 0xA8014000
C66xx_0: GEL Output: BOOTCFG_BOOTCOMPLETE ---> 0x00000001

C66xx_0: GEL Output: C6678 Core 0 ---> Boot process Completed
C66xx_0: GEL Output: C6678 Core 1 ---> Boot in process. Not Complete
C66xx_0: GEL Output: C6678 Core 2 ---> Boot in process. Not Complete
C66xx_0: GEL Output: C6678 Core 3 ---> Boot in process. Not Complete
C66xx_0: GEL Output: C6678 Core 4 ---> Boot in process. Not Complete
C66xx_0: GEL Output: C6678 Core 5 ---> Boot in process. Not Complete
C66xx_0: GEL Output: C6678 Core 6 ---> Boot in process. Not Complete
C66xx_0: GEL Output: C6678 Core 7 ---> Boot in process. Not Complete
C66xx_0: GEL Output: *******************************************************************************************************
C66xx_0: GEL Output: ********************************** C6678 RESET STATUS ******************************************************
C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: BOOTCFG_RESET_STAT ---> 0x80000000

C66xx_0: GEL Output: C6678 Global Reset ---> Device received a global reset
C66xx_0: GEL Output: C6678 Core 0 Reset ---> Core 0 has not received a local reset
C66xx_0: GEL Output: C6678 Core 1 Reset ---> Core 1 has not received a local reset
C66xx_0: GEL Output: C6678 Core 2 Reset ---> Core 2 has not received a local reset
C66xx_0: GEL Output: C6678 Core 3 Reset ---> Core 3 has not received a local reset
C66xx_0: GEL Output: C6678 Core 4 Reset ---> Core 4 has not received a local reset
C66xx_0: GEL Output: C6678 Core 5 Reset ---> Core 5 has not received a local reset
C66xx_0: GEL Output: C6678 Core 6 Reset ---> Core 6 has not received a local reset
C66xx_0: GEL Output: C6678 Core 7 Reset ---> Core 7 has not received a local reset
C66xx_0: GEL Output: *******************************************************************************************************
C66xx_0: GEL Output: ********************************** C6678 EFUSE AUTOLOAD STATUS ******************************************************
C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: PLLCONTROL_FUSE_ERR ---> 0x00000000

C66xx_0: GEL Output: Efuse Autoload ##PASS##
C66xx_0: GEL Output: *******************************************************************************************************
C66xx_0: GEL Output: ********************************** C6678 MAIN PLL CONFIGURATION ******************************************************
C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: BOOTCFG_MAINPLLCTL0 ---> 0x09000000
C66xx_0: GEL Output: BOOTCFG_MAINPLLCTL1 ---> 0x00000040

C66xx_0: GEL Output: PLLD : 0
C66xx_0: GEL Output: PLLM[12:6] : 0
C66xx_0: GEL Output: BYPASS : 0
C66xx_0: GEL Output: BWADJ[7:0] : 9
C66xx_0: GEL Output: BWADJ[11:8] : 0
C66xx_0: GEL Output: *******************************************************************************************************
C66xx_0: GEL Output: ********************************** PLL CONTROLLER CONFIGURATION SNAPSHOT **************************************
C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: *************************** PLL Control Register (PLLCTL) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLCTL ---> 0x00000041

C66xx_0: GEL Output: PLLEN[0] ---> PLL mode. Dividers PREDIV and PLL are ##not bypassed##
C66xx_0: GEL Output: PLLPWRDN[1] ---> PLL is ##operational##
C66xx_0: GEL Output: PLLRST[3] ---> PLL reset is ##released##
C66xx_0: GEL Output: PLLENSRC[5] ---> PLLEN bit is ##enabled##

C66xx_0: GEL Output: *************************** PLL Multiplier Control Register (PLLM) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLM ---> 0x00000013

C66xx_0: GEL Output: PLLM[5:0] ---> 19 multiplier rate

C66xx_0: GEL Output: *************************** PLL Pre-Divider Registers (PREDIV) ****************************

C66xx_0: GEL Output: PLLCONTROL_PREDIV ---> 0x00000000

C66xx_0: GEL Output: RATIO[4:0] ---> /1. Divide frequency by 1
C66xx_0: GEL Output: PREDEN[15] ---> Pre-divider is **disabled**. No clock output

C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV1) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV1 ---> 0x00008000
C66xx_0: GEL Output: RATIO[4:0] ---> /1. Divide frequency by 1
C66xx_0: GEL Output: D1EN[15] ---> Divider1 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV2) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV2 ---> 0x00008002
C66xx_0: GEL Output: RATIO[4:0] ---> /3. Divide frequency by 3
C66xx_0: GEL Output: D2EN[15] ---> Divider2 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV3) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV3 ---> 0x00008001
C66xx_0: GEL Output: RATIO[4:0] ---> /2. Divide frequency by 2
C66xx_0: GEL Output: D3EN[15] ---> Divider3 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV4) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV4 ---> 0x00008002
C66xx_0: GEL Output: RATIO[4:0] ---> /3. Divide frequency by 3
C66xx_0: GEL Output: D4EN[15] ---> Divider4 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV5) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV5 ---> 0x00008004
C66xx_0: GEL Output: RATIO[4:0] ---> /5. Divide frequency by 5
C66xx_0: GEL Output: D5EN[15] ---> Divider5 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV6) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV6 ---> 0x0000803F
C66xx_0: GEL Output: RATIO[4:0] ---> /64. Divide frequency by 64
C66xx_0: GEL Output: D6EN[15] ---> Divider6 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV7) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV7 ---> 0x00008005
C66xx_0: GEL Output: RATIO[4:0] ---> /6. Divide frequency by 6
C66xx_0: GEL Output: D7EN[15] ---> Divider7 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV8) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV8 ---> 0x0000803F
C66xx_0: GEL Output: RATIO[4:0] ---> /64. Divide frequency by 64
C66xx_0: GEL Output: D8EN[15] ---> Divider8 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV9) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV9 ---> 0x0000800B
C66xx_0: GEL Output: RATIO[4:0] ---> /12. Divide frequency by 12
C66xx_0: GEL Output: D9EN[15] ---> Divider9 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV10) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV10 ---> 0x00008002
C66xx_0: GEL Output: RATIO[4:0] ---> /3. Divide frequency by 3
C66xx_0: GEL Output: D10EN[15] ---> Divider10 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV11) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV11 ---> 0x00008005
C66xx_0: GEL Output: RATIO[4:0] ---> /6. Divide frequency by 6
C66xx_0: GEL Output: D11EN[15] ---> Divider11 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV12) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV12 ---> 0x00008003
C66xx_0: GEL Output: RATIO[4:0] ---> /4. Divide frequency by 4
C66xx_0: GEL Output: D12EN[15] ---> Divider12 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV13) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV13 ---> 0x00008007
C66xx_0: GEL Output: RATIO[4:0] ---> /8. Divide frequency by 8
C66xx_0: GEL Output: D13EN[15] ---> Divider13 is ##enabled##
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV14) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV14 ---> 0x00000000
C66xx_0: GEL Output: RATIO[4:0] ---> /1. Divide frequency by 1
C66xx_0: GEL Output: D14EN[15] ---> Divider14 is **disabled**. No clock output
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV15) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV15 ---> 0x00000000
C66xx_0: GEL Output: RATIO[4:0] ---> /1. Divide frequency by 1
C66xx_0: GEL Output: D15EN[15] ---> Divider15 is **disabled**. No clock output
C66xx_0: GEL Output: *************************** PLL Controller Divider Register (PLLDIV16) ****************************

C66xx_0: GEL Output: PLLCONTROL_PLLDIV16 ---> 0x00000000
C66xx_0: GEL Output: RATIO[4:0] ---> /1. Divide frequency by 1
C66xx_0: GEL Output: D16EN[15] ---> Divider16 is **disabled**. No clock output

C66xx_0: GEL Output: *************************** Clock Enable Control Register (CKEN) ****************************

C66xx_0: GEL Output: PLLCONTROL_CKEN ---> 0x00000000

C66xx_0: GEL Output: AUXEN[0] ---> **Disable** AUXCLK

C66xx_0: GEL Output: *************************** Reset Control Register (RSTCTRL) ****************************

C66xx_0: GEL Output: PLLCONTROL_RSCTRL ---> 0x00010003

C66xx_0: GEL Output: SWRST[16] ---> Software reset is ##not asserted##

C66xx_0: GEL Output: *************************** Reset Configuration Register (RSTCFG) ****************************

C66xx_0: GEL Output: PLLCONTROL_RSCFG ---> 0x00000000

C66xx_0: GEL Output: WDTYPE[1](Core0 Watchdog Timer initiates a reset of type) ---> Hard Reset (default)
C66xx_0: GEL Output: WDTYPE[2](Core1 Watchdog Timer initiates a reset of type) ---> Hard Reset (default)
C66xx_0: GEL Output: WDTYPE[3](Core2 Watchdog Timer initiates a reset of type) ---> Hard Reset (default)
C66xx_0: GEL Output: WDTYPE[4](Core3 Watchdog Timer initiates a reset of type) ---> Hard Reset (default)
C66xx_0: GEL Output: RESET(bar)TYPE[12] (RESET(bar)initiated Reset) ---> Hard Reset (default)
C66xx_0: GEL Output: PLLCTLRSTTYPE[13] ( PLL controller initiated Reset) ---> Hard Reset (default)

C66xx_0: GEL Output: *************************** Reset Isolation Register (RSISO) ****************************

C66xx_0: GEL Output: PLLCONTROL_RSISO ---> 0x00000000

C66xx_0: GEL Output: MOD_ISO[3] ---> AIF2 **Not** reset isolated
C66xx_0: GEL Output: MOD_ISO[8] ---> Smart-Reflex(SR) **Not** reset isolated
C66xx_0: GEL Output: MOD_ISO[9] ---> SRIO **Not** reset isolated

C66xx_0: GEL Output: *************************** PLL Post-Divider Control Register (POSTDIV) ****************************

C66xx_0: GEL Output: PLLCONTROL_POSTDIV ---> 0x00000000

C66xx_0: GEL Output: RATIO[4:0] ---> /1. Divide frequency by 1
C66xx_0: GEL Output: PREDEN[15] ---> Post-divider is **disabled**. No clock output

C66xx_0: GEL Output: *************************** PLL Secondary Control Register (SECCTL) ****************************

C66xx_0: GEL Output: PLLCONTROL_SECCTL ---> 0x00090000

C66xx_0: GEL Output: OUTPUT_DIVIDE[22:19] ---> /2. Divide frequency by 2
C66xx_0: GEL Output: BYPASS[23] ---> Main PLL Bypass ##disabled##

C66xx_0: GEL Output: *******************************************************************************************************
C66xx_0: GEL Output: ********************************** PLL CONTROLLER STATUS SNAPSHOT **************************************
C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: *************************** Clock Status Register (CKSTAT) ****************************

C66xx_0: GEL Output: PLLCONTROL_CKSTAT ---> 0x00000000

C66xx_0: GEL Output: AUXON[0] ---> AUXCLK is **gated**

C66xx_0: GEL Output: *************************** SYSCLK Status Register (SYSTAT) ****************************

C66xx_0: GEL Output: PLLCONTROL_SYSTAT ---> 0x00001FFF

C66xx_0: GEL Output: SYS[1]ON ---> SYSCLK1 is ##on##
C66xx_0: GEL Output: SYS[2]ON ---> SYSCLK2 is ##on##
C66xx_0: GEL Output: SYS[3]ON ---> SYSCLK3 is ##on##
C66xx_0: GEL Output: SYS[4]ON ---> SYSCLK4 is ##on##
C66xx_0: GEL Output: SYS[5]ON ---> SYSCLK5 is ##on##
C66xx_0: GEL Output: SYS[6]ON ---> SYSCLK6 is ##on##
C66xx_0: GEL Output: SYS[7]ON ---> SYSCLK7 is ##on##
C66xx_0: GEL Output: SYS[8]ON ---> SYSCLK8 is ##on##
C66xx_0: GEL Output: SYS[9]ON ---> SYSCLK9 is ##on##
C66xx_0: GEL Output: SYS[10]ON ---> SYSCLK10 is ##on##
C66xx_0: GEL Output: SYS[11]ON ---> SYSCLK11 is ##on##
C66xx_0: GEL Output: SYS[12]ON ---> SYSCLK12 is ##on##

C66xx_0: GEL Output: *************************** Reset Type Status Register (RSTYPE) ****************************

C66xx_0: GEL Output: PLLCONTROL_RSTYPE ---> 0x00000001

C66xx_0: GEL Output: POR[0] ---> Power-on reset **was** the last reset to occur
C66xx_0: GEL Output: RESET(bar)[1] ---> RESET(bar)initiated Reset ##was not## the last reset to occur
C66xx_0: GEL Output: PLLCTLRST[2] ---> PLLCTL initiated Reset ##was not## the last reset to occur
C66xx_0: GEL Output: WDRST[1] ---> Core0 watchdog Timer initiated Reset ##was not## the last reset to occur
C66xx_0: GEL Output: WDRST[2] ---> Core1 watchdog Timer initiated Reset ##was not## the last reset to occur
C66xx_0: GEL Output: WDRST[3] ---> Core2 watchdog Timer initiated Reset ##was not## the last reset to occur
C66xx_0: GEL Output: WDRST[4] ---> Core3 watchdog Timer initiated Reset ##was not## the last reset to occur
C66xx_0: GEL Output: EMURST[0] ---> Emulation initiated Reset ##was not## the last reset to occur

C66xx_0: GEL Output: *******************************************************************************************************
C66xx_0: GEL Output: ********************************** C6678 BRIDGE SCAN RESULTS ******************************************************
C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: Bridge5 scan Test PASSED
C66xx_0: GEL Output: Bridge6 scan Test PASSED
C66xx_0: GEL Output: Bridge7 scan Test PASSED
C66xx_0: GEL Output: Bridge8 scan Test PASSED
C66xx_0: GEL Output: Bridge9 scan Test PASSED
C66xx_0: GEL Output: Bridge10 scan Test PASSED
C66xx_0: GEL Output: Bridge2 scan Test PASSED
C66xx_0: GEL Output: Bridge3 scan Test PASSED
C66xx_0: GEL Output: No Errors detected in the bridge scan

C66xx_0: GEL Output: BRIDGES NOT TESTED: Bridge1 and Bridge4

C66xx_0: GEL Output: *******************************************************************************************************
C66xx_0: GEL Output: ********************************** C6678 SLAVE SCAN RESULTS ******************************************************
C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: SPI Slave scan Test PASSED
C66xx_0: GEL Output: BOOT_ROM Slave scan Test PASSED
C66xx_0: GEL Output: COREPAC0 Slave scan Test PASSED
C66xx_0: GEL Output: COREPAC1 Slave scan Test PASSED
C66xx_0: GEL Output: COREPAC2 Slave scan Test PASSED
C66xx_0: GEL Output: COREPAC3 Slave scan Test PASSED
C66xx_0: GEL Output: COREPAC4 Slave scan Test PASSED
C66xx_0: GEL Output: COREPAC5 Slave scan Test PASSED
C66xx_0: GEL Output: COREPAC6 Slave scan Test PASSED
C66xx_0: GEL Output: COREPAC7 Slave scan Test PASSED
C66xx_0: GEL Output: MSMC_SMS Slave scan Test PASSED
C66xx_0: GEL Output: MSMC_SES Slave scan Test PASSED
C66xx_0: GEL Output: No Errors detected in the SCR Slaves error scan

C66xx_0: GEL Output: SLAVES NOT TESTED: SRIO_Slave, PCIe_Slave, HYPERBRIDGE_Slave, QMSS_Slave

C66xx_0: GEL Output: *************************** C6678 Silicon Revision (PG 1.0 OR PG 2.0) ****************************

C66xx_0: GEL Output: MM_REVID[31:0] - 0x00080001

C66xx_0: GEL Output: Silicon Revision UNKNOWN

Rahul,

I'm connected to the board through CCS and when I hit the reset button on the board, I can step through the assembly of the Bootrom (0x20b00000). But of course, this is taking forever. I set a breakpoint at my __c_init but it is never getting there. If you could tell me an interesting breakpoint in the Bootrom to set, I might be able to figure something out.. I do see in my UART:

IBL: Booting from NOR

I wanted to just see debug logs corresponding to the PLL and bootloader. It does show that the boot completed so I am little confused why the Program counter is at 0x20b00000 which is the base of the ROM bootloader. The DEVSTAT register indicates I2C boot which  is correct as you are booting the IBL first but the Main PLL registers are indicating that they have not been programmed:

C66xx_0: GEL Output: PLLD : 0

C66xx_0: GEL Output: PLLM[12:6] : 0

C66xx_0: GEL Output: BYPASS : 0

C66xx_0: GEL Output: BWADJ[7:0] : 9

C66xx_0: GEL Output: BWADJ[11:8] : 0

Can you provide a way in which I can reproduce this issue with my setup? 

Regards,

Rahul 

The ROM bootloader symbol for bootMainSPI is at 0x20b08750 and the bootExit is defined at 0x20b08ca8 and hardware spi transfer is at 0x20b0a1c0. I would set hardware break point at those values to check if the image is being transferred from SPI into device memory.

Regards,
Rahul

Rahul,

I am not reaching any of those breakpoints.  Not sure what else to try.

Rahul, would it be possible for you to send me a simple RTSC project (CCSv6) that I can burn to Flash and boot? I would expect the post build steps to generate whatever file that needs to be burned and that I can use norwriter_evmc6678l to burn it. My eval board is a TMDSEVM6678LE

David,

Sorry, I was sidetracked due to a different task yesterday so I wasn`t able to get back to you. I have received your TI RTOS image and will try to boot it on my EVM and get back to you with the instructions to flash and boot the application.

Regards,
Rahul

Rahul,

I was looking at the .bin file that gets generated and it looks odd at the end compared to the .bin file that my non-RTSC project generates.   I'm wondering if my .rmd file needs something different for the RTSC project?  Here's what's in it:

SWIT_Core1_5.out

-a
-boot
-e _c_int00

ROMS
{
   ROM1: org=0x0800000, len=0x080000, romwidth=32, memwidth=32
   files={SWIT_Core1_5.btbl}
} 

Rahul,

I found a problem. The .btbl file that gets generated by the TI hex6x utility is putting the wrong number of bytes for a section in the boot table. This causes the bootloader to look at the wrong place for the next header so it gets a bad byte count and load address and crashes. I was able to hexedit the .btbl file and then generate the .bin file from that and it loaded just fine from Flash. But why is this happening? Does it have something to do with RTSC or the size of the .out file? I could parse the .out file and see if the error is also in that (once I learn the ELF format).

So, any ideas?

David,

Thanks for providing your findings. The hex6x tool is supported by the compiler forums. I will move this to the compiler forums so that they can comment why the tool is generating incorrect data.

Please provide the compiler version and information and indicate what section data is incorrectly generated so that the compiler team can comment on the specifics.

Regards,
Rahul

I'm using CCS version 6.1.2.00015

The compiler is TI v8.1.3  (C6000 family)

I'm not positive which section is getting the bad byte count, but my guess is the .switch section?   It is the 4th section that is getting corrupted and here's what I see when I build:

Translating to ASCII-Hex format...

"SWIT_Core1_5.out" .text ==> (BOOT TABLE)

"SWIT_Core1_5.out" .cinit ==> (BOOT TABLE)

"SWIT_Core1_5.out" .const ==> (BOOT TABLE)

"SWIT_Core1_5.out" .switch ==> (BOOT TABLE)

"SWIT_Core1_5.out" .vecs ==> (BOOT TABLE)

David

Use the ofd6x utility to read the ELF file.

How do I use that utility?

Rahul,

At the advice of "Archeologist", I ran the ofd6x utility and I can see that the bad section is .const. It shows it as being 0x2d42, but if you count the bytes in that section (24 bytes per line * number of lines, etc) you get 0x2d44. If I manually edit the .btbl file and change it to 0x2d44, the program loads from flash and runs correctly.

Section Information

id name load addr run addr size align alloc
-- ---- --------- -------- ---- ----- -----
0 (no name) 0x00000000 0x00000000 0x0 0 N
1 .csl_vect 0x00000000 0x00000000 0x0 1 N
2 .text 0x00800000 0x00800000 0x16080 32 Y
3 .neardata 0x00826268 0x00826268 0x8 4 Y
4 .rodata 0x00826270 0x00826270 0x0 1 Y
5 .bss 0x00826270 0x00826270 0x0 1 Y
6 .stack 0x00821b10 0x00821b10 0x2000 8 Y
7 .cinit 0x00826600 0x00826600 0xfc0 8 Y
8 .cio 0x00826110 0x00826110 0x120 8 Y
9 .const 0x0081edc8 0x0081edc8 0x2d42 8 Y
10 .data 0x00000000 0x00000000 0x0 1 Y
11 .switch 0x00826230 0x00826230 0x38 4 Y

This forum thread discusses a case where hex6x correctly adds some padding bytes to a section.  Perhaps that is the case here.

Thanks and regards,

-George

Well, that might be the case here. The .out file says that there are 0x2D42 bytes in the section but I see 0x2D44 bytes in the .btbl file. And the 2 extra bytes are 0's. Unfortunately, the header in the .btbl file still says there are 0x2D42 bytes instead of saying 0x2D44. And that causes problems when I convert it to a .bin file and also when I try to load it. Shouldn't the header indicate the extra 2 bytes?

George, I also have an issue with my core0 application. I'm writing the .out file to NOR flash for the IBL to load. This worked fine until I converted my application to a RTSC project, now it doesn't load. Is it a similar problem? How can I fix this? I'm trying to run out of L2SRAM if it makes a difference.

David Hague said:

George, I also have an issue with my core0 application. I'm writing the .out file to NOR flash for the IBL to load. This worked fine until I converted my application to a RTSC project, now it doesn't load. Is it a similar problem? How can I fix this? I'm trying to run out of L2SRAM if it makes a difference.

Unfortunately, this question is well outside my expertise.  It doesn't seem like a similar problem.  I suggest you start a new thread in the Keystone device forum.

Thanks and regards,

-George

SWIT_Core1_5.zipGeorge,

Here's the .out file zipped up.

Thanks for your help.

David

I apologize for the delay.

Unfortunately, I cannot reproduce the problem with this .out file.  The problem section is .const.  Here is the start of that section in the .btbl file (the hex utility output) ...

00 00 2E 1E
00 81 FA C8
69 5F 41 00
69 74 69 6E

I broke it up into 32-bits per line, for easy reference.  Line 1 is the length.  Line 2 is the address.  The rest is data.  This exactly matches what is in the .out file for .const.  One way to see this is with the ofd6x output ...

 Section Information

    id name                      load addr  run addr      size align alloc
    -- ----                      ---------  --------      ---- ----- -----
<skip some lines>
     9 .const                    0x0081fac8 0x0081fac8  0x2e1e     8   Y

Thanks and regards,

-George