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Bug Report : C6000 Intrinsics implementation for PC

moshe haim
Prodigy 10 points

Hello,

     I am writing code for the C64x Core. I found it very useful to use an implementation of the intrisincs for PC host on which I can develope and Debug my code before Working on the DSP. My team was using an old implementation we found in an article from TI. in recent time i found the following link:

https://www-a.ti.com/downloads/sds_support/applications_packages/c_intrinsics_host_port/index.htm

where one can find a new software package to enablecode development on a PC Host. while using the software i found that the implementation of _mpylir is not bit exact with the results i get on the DSP. for example: _mpylir(-1, 2147467264) will return a value of -65536 on the PC while on the DSP, you will get -65535. similarly _mpylir(-1, 2147434496) will return -65535 on PC and -65534 on DSP. 

the TI support have directed me here to find an answer. for now I am using a mix of the old code and the new one.

is there a new version planned for this software package ?

  • 0
    TI__Guru**** 173310 points

    Moshe,

    At this time, I'm not certain if a new version of this software package is in the plans, but I will check and we will update this post. We will also look into the reported bug and post an update once it is confirmed.

  • 0
    TI__Guru**** 253270 points

    moshe haim said:
    is there a new version planned for this software package ?

    This particular bug has already been reported and fixed in internal development versions.  Since it is short, I'll publish the corrected version of these intrinsics here.  Note _mpyhir had to be fixed as well.

    int32 _mpylir(int32 a, int32 b)
{
  union reg32 a32;
  union reg64 a64, b64, y64;

  a32.x1 = a;
  if ((a32.x2.lo == MIN_INT16) && (b == MIN_INT32))
  {
    CSR |= DSP_CSR_SAT;
    return MAX_INT32;
  }

  a64.x1_ll = a32.x2.lo;
  b64.x1_ll = b;
  y64.x1_ll = (a64.x1_ll * b64.x1_ll + 0x4000) >> 15;

  return y64.x2.lo;
}

int32 _mpyhir(int32 a, int32 b)
{
  union reg32 a32;
  union reg64 a64, b64, y64;

  a32.x1 = a;
  if ((a32.x2.hi == MIN_INT16) && (b == MIN_INT32))
  {
    CSR |= DSP_CSR_SAT;
    return MAX_INT32;
  }

  a64.x1_ll = a32.x2.hi;
  b64.x1_ll = b;
  y64.x1_ll = (a64.x1_ll * b64.x1_ll + 0x4000) >> 15;

  return y64.x2.lo;
}

    I hope this is a practical workaround for now.

    Thanks and regards,

    -George