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Tool/software: TI C/C++ Compiler
I have code like this:
[A] __R30 = ctrl ;
[B] myvar = (myexpr) ; // 4 cycles
[C] __delay_cycles(4) ; // 4 cycles
[D] result = __R31 ; // 8 cycles delay
Point [D] must be 40ns = 8 cycles later then [A].
To not waste time, I moved some calculation to [B].
[B] is 4 cycles, so this worked until the optimizer "clpru -O3" moved [B] before [A].
Executing [B], [A], [C], [D] is only 4 cycles, so error.
Questions:
- what can I do to temporarily prohibit code reorder between [A] and [D] ?
- is guaranteed, that the optimizer always lets __delay_cycles() stay in place between [A] and [D] ?
Maybe here's a potential target collision: the PRUs shall execute code in deterministic timing, but the optimizer may scramble everything.
Proposal: make a pair of two intriniscs __delay_start() and __delay_end(), which tells the compiler between which points I need the delay:
Then the optimizer could arranged code accordingly.
__delay_start() ;
__R30 = ctrl ;
myvar = (myexpr) ;
__delay_end(8) ; // need 8 cycles from __delay_start() to here
result = __R31 ;
Thank you for bringing this problem to our attention. To address it, I filed CODEGEN-4843 in the SDOWP system. This entry does not report a bug, but requests an improvement to the compiler. At this point, I avoid prescribing solutions to problem. I focus instead on a clear statement of what is required. That is why I titled the entry ...
Create method to separate volatile accesses by N cycles, while filling those cycles with useful instructions.
You are welcome to follow this entry with the SDOWP link below in my signature.
Thanks and regards,
-George