Tool/software: TI C/C++ Compiler
I can see that ARM-CGT-17_18.1.3.LTS includes a fix for the __delay_cycles() intrinsic--thank you!
For CPUs which have caching (such as the TMS570LC4357, which implements an ARM Cortex-R5f), how does caching impact the __delay_cycles() timing?
Does the implementation assume caching is enabled, and if caching actually is disabled then __delay_cycles() will take more CPU cycles than specified? (Similar to the documented behavior, where the timing of __delay_cycles() assuming 0 wait states.)
Does the implementation assume caching is not enabled, and if caching actually is enabled then __delay_cycles() might execute in fewer CPU cycles than specified?
(Or were you able to pull off some kind of magic where the cycle count timing is more-or-less independent of the cache state?)
--thx
