CCS/UCD3138PFCEVM-026: PWR026_PFC

The 127 is a number to see if the positive cycle has gone on for two long, Each count represents 100 usec, so 127 would be 12.7 milliseconds.  Even at 50 Hz, it should not be positive more than 10 milliseconds.  So in that case, we try to do something to make the code work for DC.  I don't think we have actually tested it at DC, however.

The 3ff is the full range of the EADC DAC, so we are preventing a value outside the full range by clamping it to that level.  

Thanks for your help！