CCS/TMS320F28335: TMS320F28335

Anu,

Have you gone through One-Day workshop on the device? It goes through interrupt service routine.

https://training.ti.com/c2000-f2833x-microcontroller-workshop

I have searched the manual, but i wasn't able to find out about ISR. 

Which manual you searched about ISR?

Here is the link for compiler documentation

http://www.ti.com/lit/ug/spru514p/spru514p.pdf

Have you gone through the workshop to understand better about the device?

Thanks. I can understand now. But i am not able to understand how the ISR is called in this particular code:

1. According to the SCI reference guide, the TX FIFO will generate an interrupt if the TXFFST is less than TXFFIL:

"Transmit FIFO will generate interrupt when the FIFO status bits (TXFFST4–0) are less than or equal to FIFO interrupt level bits (TXFFIL4–0)".

So here the SciaTxFifoIsr will be serviced as long as TxFifo has less than 8 words right? (Because in this code TXFFIL is written 8)

So, immediately after scia_fifo_init();  is called,  SciaRegs.SCIFFTX.all= 0xC028 is set. Hence now TXFFIL = 8 words, while TxFifo has 0 words. So ISR SciaTxFifoIsr will be entered and serviced. So SCITXBUF will be written the value of sdataA[i].

But sdata[i[] is initialized only in step 5 (after  scia_fifo_init(); is called which is in step 4). 

So what value will be written into SCITXBUF since the value of sdata[i] is written to it before its initialization?

[ Initialization is in step 5 only. But scia_fifo_init() is called in step 4 which makes the Interrupt service routine to be called as TXFFST (0 words) is  less than FIFO interrupt level bits (TXFFIL) - which has 8 words  ]

Thanks. That made me understand. I have one final doubt though, in the same SCI loopback with interrupt example.

The SCITXFIFO and SCIRXFIFO are configured as under:

SciaRegs.SCIFFTX.all=0xC028; // 1100 0000 0010 1000   //TXFFIL = 8 words,RXFFST =0

SciaRegs.SCIFFRX.all=0x0028; // 0000 0000 0010 1000   //RXFFIL = 8 words, RXFFST=0

1. My first doubt is that the Tx/RX FIFO and TX/RXBUF is only 8 bits wide --> One word. So how can they hold 8 words? If TXFFST =8, it means receive FIFO has 8 words right? How is tha possible?

2. According to the SCI reference guide, the TX FIFO will generate an interrupt if the TXFFST is less than TXFFIL

"Transmit FIFO will generate interrupt when the FIFO status bits (TXFFST4–0) are less than or equal to FIFO interrupt level bits (TXFFIL4–0)".

So data will be read from sdataA[i] array as and when a word is receive and the interrupt is serviced for all TXFFST <TXFFIL (8 words) right? 

3. But RX FIFO will generate an interrupt only if the RXFFST is more than RXFFIL

"Receive FIFO generates interrupt when the FIFO status bits (RXFFST4–0) are greater than or equal to FIFO interrupt level bits (RXFFIL4–0)".

Since in internal loopback, Tx and Rx are shorted, the same data will be received in Rx.

So data will be read from SCIRXBUF array. But the interrupt will be serviced only when RXFFST>= RXFFIL. So it implies the ISR will be run only when RXFFST reaches 8. But the FIFO itself can hold only 8 bits (1 word). So how can data be read 8 words once? Also the ISR in the example code suggests that the data read is only one word. If the interrupt is called only if RXFIFO has 8 words and only one word is read, the rest of the 7 words will never be read. So does this mean, the data is read as and when a word is received? But the definition says otherwise. (That, Interrupt is serviced only if RXFFST >= RXFFIL).

for(i=0;i<8;i++)

{
rdataA[i]=SciaRegs.SCIRXBUF.all; // Read data
}

How is this possible?

Thanks!

Anu B said:

1. My first doubt is that the Tx/RX FIFO and TX/RXBUF is only 8 bits wide --> One word. So how can they hold 8 words? If TXFFST =8, it means receive FIFO has 8 words right? How is tha possible?

Please take a look at the definition of SCIFFTX register in section 10.14.2.10.

For #2, and #3, I will recommend you to go through the SCI FIFO description in section 10.13.1.

Okay, so just a clarification.

1. So the Tx/Rx FIFO is a stack of 16x8bits, and hence it can hold 16 words.

2. And as per the configuration of Tx and Rx FIFO in the example, data will be written to SCITXBUF 1 word once.

But with FIFO enabled, TXSHF will directly be loaded after an optional delay value (SCIFFCT); TXBUF wont be used. So what is the significance of writing in TXBUF in ISR?

3. When the SCI receives a data, RXENA (SCICTL1.0) is set, the data in the RXSHF register is transferred to the SCIRXBUF register. This action sets the RXRDY flag (SCIRXST, bit 6) and if RX/BK INT ENA bit (SCICTL2.1) is set, an interrupt is initiated.

But with FIFO enabled, interrupt will be serviced if RXFFIL is set and RXFFIENA is enabled. RXFFIENA is set once the number of words in RXFIFO reaches 8; and the first word is read.

Since it is infinite loop, eventually all words in RXFIFO would be read. But what about the case when its not a infinite loop? Then RXFFIL should be set as 1 right? So that each word is read as and when it is received?

Anu,

#1 : Yes

#2 : Please take a block diagram of SCI module (section 10.2). It explains the data/interrupt flow.

#3 : You can do that if your application requires that, but there will be CPU overhead, too many interrupts. (Refer Table 10-17)

Okay. Thanks a lot!