Hi TI's team,
Hope you have a nice day.
I have found grid side voltage (VGRID_A,VGRID_B,VGRID_C) and dc-link voltage(VBUS_ADC) sampling have been triggered four times in each cycle. But the inverter side voltage and other sampling are only triggered once in each cycle.
What's the major reason and major concerns about these difference?
#define TINV_VBUS_READ (float32_t)(TINV_VBUS_READ_1 + TINV_VBUS_READ_2 + TINV_VBUS_READ_3 + TINV_VBUS_READ_4) * (0.25f)
#define TINV_VGRID_A_READ (float32_t)(TINV_VGRID_A_READ_1 + TINV_VGRID_A_READ_2 + TINV_VGRID_A_READ_3 + TINV_VGRID_A_READ_4) * (0.25f)
#define TINV_VGRID_B_READ (float32_t)(TINV_VGRID_B_READ_1 + TINV_VGRID_B_READ_2 + TINV_VGRID_B_READ_3 + TINV_VGRID_B_READ_4) * (0.25f)
#define TINV_VGRID_C_READ (float32_t)(TINV_VGRID_C_READ_1 + TINV_VGRID_C_READ_2 + TINV_VGRID_C_READ_3 + TINV_VGRID_C_READ_4) * (0.25f)