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WEBENCH® Tools/LM5088-Q1: Webbench EAGLE export issues

Part Number: LM5088-Q1

Tool/software: WEBENCH® Design Tools

Hello TI Webbench developers,

I would like to report some issues to the Webbench EAGLE export feature, because in the current form it is hardly usable.

I would suggest to merge the SCH and PCB export (only for the EAGLE export) because in EAGLE the SCH and BRD should have the same name to be opened simultenaously. When downloading them separately they got a name with the timestamp so either one will need to be renamed.

After moving the SCH and BRD to the same directory and renaming them to the same basename the following errors need to came over:

There are some attributes which got redefined and the EAGLE breaks the parsing of these schematics:

<technology name="">
                                 <attribute name="Cap" value="0" constant="no" />
                                 <attribute name="ESR" value="0" constant="no" />
                                 <attribute name="IRMS" value="0" constant="no" />
                                 <attribute name="VDC" value="0" constant="no" />
                                 <attribute name="Manufacturer_Part_Number" value="GENERIC_CAPACITOR" constant="no" />
                                 <attribute name="Vendor" value="Unknown" constant="no" />
                                 <attribute name="Foot_Print_Area" value="0.0" constant="no" />
                                 <attribute name="A" value="0.0" constant="no" />
                                 <attribute name="B" value="0.0" constant="no" />
                                 <attribute name="C" value="0.0" constant="no" />
                                 <attribute name="Part_Number" value="CUSTOM" constant="no" />
                                 <attribute name="D" value="0.0" constant="no" />
                                 <attribute name="Thermal_ID" value="CUSTOM" constant="no" />
                                 <attribute name="Component_Type_Index" value="30" constant="no" />
                                 <attribute name="Mount" value="?" constant="no" />
                                 <attribute name="TaMin" value="0.0" constant="no" />
                                 <attribute name="VDC" value="0.0" constant="no" />
                                 <attribute name="Derated_Cap" value="2.1E-6" constant="no" />
                                 <attribute name="Technology" value="Ceramic" constant="no" />
                                 <attribute name="Dimension_X" value="0.0" constant="no" />
                                 <attribute name="Thermal_Status" value="N" constant="no" />
                                 <attribute name="Dimension_Y" value="0.0" constant="no" />
                                 <attribute name="Dimension_Z" value="0.0" constant="no" />
                                 <attribute name="TaMax" value="0.0" constant="no" />
                                 <attribute name="Schematic_mapping_symbol" value="WB_CAPACITOR" constant="no" />
                                 <attribute name="Component_Type" value="Capacitor" constant="no" />
                                 <attribute name="Part_ID" value="18" constant="no" />
                                 <attribute name="Budget_Price" value="0.0" constant="no" />
                                 <attribute name="ESR" value="0.0" constant="no" />
                                 <attribute name="Tolerance" value="0.0" constant="no" />
                                 <attribute name="Quantity" value="1" constant="no" />
                                 <attribute name="Quantity_In_stock" value="0" constant="no" />
                                 <attribute name="IRMS" value="0.0" constant="no" />
                                 <attribute name="Series" value="?" constant="no" />
                                 <attribute name="Cap" value="2.0833333333333334E-6" constant="no" />
                                 <attribute name="Total_Derated_Cap" value="2.1E-6" constant="no" />
                                 <attribute name="Manufacture" value="CUSTOM" constant="no" />
                                 <attribute name="Manufacturer_Name" value="CUSTOM" constant="no" />
                              </technology>

After removing these duplicate attributes the EAGLE will report that the annotation is disabled because the SCH and BRD differs (see in the ERC result):

The problem sources are the following:

Some parts has different name in the SCH and BRD (CIN - CIN_1, CRST - CDTRH). (This could be solved by renaming those parts.)

The problem with the GND2, GND3, IOUT is different. These are symbol only (should appaer only in the schematic) parts I think.

For these devices an _EXTERNAL_ attribute need to be added and the package reference and the connections need to be removed:

The VOUT is a TP-1502 device which exists only on the board, in the schematic the symbol does not exported. We can get rid by deleting it from the PCB since it is covered a bigger VIA.

After correcting these issues we have to fix the attribute missing parts:

For e.g.:

To overcome this  have just removed the device attributes from the SCH parts.

After this it turned out that different library names used in the PCB and SCH:

After fixing the library name mismatch it turns out that the device values are not present in the BRD:

After copying the values either manually or via ULP to the PCB we end up in the following errors:

This is because different footprints are exported to the sch and brd:

SCH:

BRD:

Of course the BRD is correct I do not even know how the SCH got there: it is simply two TH pads.

After fixing the footprints in the SCH the schematic parsing will be broken (it might be possible that this is only related to this design):

The CDTHR in the SCH refers to a CUSTOM1 device which refers to a non existing package (GEN_CAP):

By looking into the PCB it turns out that it should be 0805.

It will then claim about the VIN and the GND parts. Simply remove them from the PCB since the pads does their job well.

Then we will get a load of fallen apart errors:

These issues could be either solved by placing junctions on the net crosses or where it does not solves it with redrawing the nets.

After this point we got back the F/B annotation and we got a working design.

Additional export hints:

  • The EAGLE uses 0.006 inch width nets in the schematic by default. It would be great if the exported schematics would follow this.
  • Use the default layers and their colors (left is Webbench export, right is EAGLE default):

  • The EAGLE also claims about redefining layers when opening the BRD file:
line 34: ignoring redefinition of  number="49" in tag <layer>
line 35: ignoring redefinition of  number="49" in tag <layer>
line 36: ignoring redefinition of  number="49" in tag <layer>
line 37: ignoring redefinition of  number="49" in tag <layer>
line 40: ignoring redefinition of  number="21" in tag <layer>
  • It would be great if the schematic pins/nets would be aligned to the 0.1 inch grid which is the recommended
  • It would be great if junctions would be placed on the net intersections.

The downloaded and the resulted files are attached below: