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TINA/Spice/UCC27712: UCC27712 outputs skip cycles or flatline with trivial circuit changes

Part Number: UCC27712
Other Parts Discussed in Thread: TINA-TI,

Tool/software: TINA-TI or Spice Models

I have a 12V TO 5V 500kHz synchronous buck converter compensator followed by a PWM generator comparator producing 3.3V true and complementary PWM outputs into HI and HL of the UCC27712, which is used to drive high- and low-side NFETs. The boost circuitry on HB, HS, HO, and LO follow the UCC27712 datasheet  example very closely and the circuit simulates fine much of the time. However, with what should be trivial circuit changes I get unexpected simulation results.  For example, when I change the datasheet boost diode from a 600V to a similar 50V part the UCC27712 outputs never begin changing in response to the complementary PWM inputs and the circuit essentially flat lines through the entire simulation. With minor circuit tweaks, the UCC27712 outputs sometimes toggle and the buck converter works, but the USS27712  occasionally skips cycles, apparently at random. Am I missing something fundamental about the part operation, or is this, perhaps, a simulator or model problem?

  • Keith, The best approach is to isolate the problem to see it is caused by UCC itself or it is a collective effect.
    1- Did you Simulate the UCC device by ideal voltages and pulses and then make the diode change or any other changes that caused the issue?
    Also take note of the changes at various nodes when you change the diode, that might shed light on the cause, which might be external to the model(s).
    2-If you suspect it is the simulator, Have you played with tolerance and time step to find out if it effects the malfunction one way or another?
    3- Without having the exact testbench it is hard to say what might be the cause.
    Regards,
    Arash
  • The datasheet provides plots for an operating frequency up to 500kHz, but the datasheet Design Requirements Table 4 and an online component summary I found state that the component must be operated at 100kHz. Though the max clock rate is ambiguous as best as I can tell,  it may be that the problem is internal state loss due to excessive speed. Earlier, I concluded that 500kHz was not a problem because simulation at 1MHz was no different from 500kHz, though at this speed the 150ns dead time to prevent shoot through is very significant. I'd like to clock at 400kHz-750kHz so I'm moving on to a different (faster) part.