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Hello All,
We have designed our BLE product by following the guidelines as per CC26xx RF Frontends and Antennas and used AN043 PCB antenna (http://www.ti.com/litv/pdf/swra117d).
We need someone's assistance to review the layout and let us know if any issues with our design.
Anyone who can help, please share your email ID where I can send our layout.
Any help will be highly appreciated.
Regards
Lakshmikanth
Hi JXS,
Thanks for your response.
I have attached the layout omitting other sections. Please review it and let us know if any issues you find.
Thanks
Lakshmikanth. Layout_Sent_TI.pdf
Hello All,
Thanks for your support. We have modified the design as per your suggestions. I have attached for your reference.
Can someone please review it and let me know any corrections needed??
Regards
Lakshmikanth. CC2650 Layout.pdf
Hi Lakshmikanth,
Mostly ok, although you do not have any matching components for the antenna. One of the 32k load caps is not connected to ground. There seems to be two decoupling caps on the VDDR-RF pin. What is the biggest cap for?
Cheers,
Fredrik
L2, C25 and L6 are used for harmonics filtering in the reference designs. Not for antenna matching. You can do it all in once, but it complicates the matching process significantly.
The 10uF cap on VDDR must be placed close to the DCDC inductor. More information here;
http://processors.wiki.ti.com/images/8/8b/CC26xx_HW_training_Layout_Considerations.pdf
http://processors.wiki.ti.com/index.php/CC26xx_HW_Checklist
Cheers,
Fredrik
Hi Fredrik,
Thanks for you guidance. Below are some updates from our side. Please review.
1. Antenna Matching circuit added with resistance and capacitance. Latest design attached. Please confirm if location is ok.
2. As per http://processors.wiki.ti.com/index.php/CC26xx_HW_Checklist,
we should ensure that the substrate height (thickness of the dielectric layer between the layout pattern and the undelying ground plane) corresponds to the reference design being copied. For the CC2650EM-XXX reference designs, which are all 2-layer boards, the value is 0.7 mm or 30 mils. For multilayer boards, you can achieve this by placing the ground plane on the layer that most closely corresponds to this height.
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We have done a four layer board, thickness of PCB is 1.2 mm. Is that OK? Do you have any suggestions that we should give the manufacturer?
Regards
Lakshmikanth.
Hi Fredrik,
Please see our answers below.
The minimum height from the RF layer to the ground plane should be 175 um. If you fulfill that, the stack-up is ok.
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Ok. Will do that.
The output cap for the DCDC and the leftmost load cap for the 32k crystal do not seem to be connected to ground.
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Revised the layout. The latest one is attached. Please check if ok now.
Why do you have a 10 uF cap on VDDR-RF?’
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We can convert 0402 package and DNM as in reference design.
What size is the 24 MHz crystal? Does this fulfill the requirements in the CC2640 data sheet?
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We use the EPSON crystal (TSX-3225 24.0000MF20G-AC3) as mentioned in http://processors.wiki.ti.com/index.php/CC26xx_Crystals
The layout is changed. Pls check if ok now.
Regards
Lakshmikanh
Hello Fredrik,
Can you please look into it? we are waiting for your review to proceed with our layout. Please help us.
Regards
Lakshmikanth.
Hello Fredrik,
We have made four boards of the above layout.
We have followed the guidelines for trouble shooting provided by TI below link.
Here are the issues we are encountering
1) VDDR=2.378V, DCOUPL=2.1V across all four boards.
2) Flash programmer 2 unable to recognise all the four boards. (Please find attachment)
Please note the supply voltages on other pins.
VDDS=3.3V
VDDS2 = VDDS3 = 1.9V (regulated).
We are using internal DCDC mode. I will send the schematics and layout over private message.
We are not sure why internal DCDC is not working. And Flash programmer 2 is not recognising the boards. Could please assist?
Regards
Lakshmikanth