Other Parts Discussed in Thread: CC115L
hi Ti engineer
Recently, one CC113L chip was found to be abnormal, which was mainly manifested as serious packet loss. The preliminary analysis showed that the chip had to wait for a long time to receive data normally after entering RX mode. See the attachment for detailed test records.
Transmitter CC115L launches 3 packets each time by pressing, each packet interval is about 3~5ms, debug the program found that bad chip packet loss did not trigger MCU external interrupt (GDO2 pin did not give pulse)
Logic analyzer is used to monitor SPI data. SPI data of good chip is as follows:
Bad chip test status
The test found that the transmitter sent 3 packets, the good chip received normal, the bad chip only received 1 packet.
The SPI instruction data of the bad chip re-enters the receiving state after receiving the first packet:
The bad chip re-enters the SPI instruction data in the receiving state after receiving the first packet
The above data comparison found that after the bad chip received the first packet, the program sent instructions to let the chip enter RX mode, and the chip also replied that it had entered RX mode (the status data of the chip was the same as that of the good chip), but the second packet of data did not trigger the reception (GDO2 pin did not give a pulse).
Conclusion: The reason of packet loss is that the RF chip did not receive data, and the GDO2 pin did not give the received signal pulse.
